From: Stuart Sutherland (stuart@sutherland-hdl.com)
Date: Wed Sep 13 2000 - 23:58:06 PDT
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At 01:49 PM 9/13/2000, Steven Sharp wrote:
>Frankly, section 5 does not fit into the rest of the standard. It uses
>terminology that is not used anywhere else in the standard. It is my
>understanding that this was some separate paper that tried to formally
>describe the Verilog scheduling semantics. It got borrowed and thrown in
>because there was no other text available that explained anything about it,
>not because it was a complete description.
IMHO, if we cannot fix section 5 in a way that all major simulator vendors
are comfortable with, then the section 5 and all references to it should be
removed from the Verilog-2000 standard. It would be better to not specify
any event mechanism than to specify something that does not work. My
understanding is that the current specification does not match any
simulator, anyway, so it is pointless to have it in the standard.
Stu
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Stuart Sutherland Sutherland HDL Inc.
stuart@sutherland-hdl.com 22805 SW 92nd Place
phone: 503-692-0898 Tualatin, OR 97062
www.sutherland-hdl.com
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