From: Dennis Marsa (drm@xilinx.com)
Date: Thu Aug 16 2001 - 09:00:02 PDT
The following reply was made to PR errata/16; it has been noted by GNATS.
From: Dennis Marsa <drm@xilinx.com>
To: btf-bugs@boyd.com
Cc: btf@boyd.com
Subject: Re: errata/16: 19.7 `line - meaning of level parameter is unclear
Date: Thu, 16 Aug 2001 09:52:10 -0600
Shalom Bresticker wrote:
> > Since this directive was envisioned to be used by a
> > source code generator (preprocessor, source to source translator, etc.)
> > the requirement of the parameters was not considered a hardcase. You are
> > correct, it is not controlling anything; nor would you want it to.
>
> Again, it looks to me to be a confusion between a compiler DIRECTIVE,
> which TELLS the compiler to DO something, on the one hand,
> and an informative preprocessor output on the other.
But it is a directive. A tool must update its current file/linenumber
state upon seeing a `line directive with the info it provides.
> If, for CPP, 'linenum' and "filename" were enough, why does Verilog need 'level' as well ?
> What does it add ? Why can't it just be a comment ?
It would seem to me, one application of the level information would be
to keep track of all currently active source files on a stack, so that when
you issue a message you could provide a trail of include files:
Error: You messed up! at file: XXX line: YYY
included from file: XXX line: YYY
included from file: XXX line: YYY
...
The level number would guide you whether to push/pop or leave your stack alone.
Dennis
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