From: Daryl Stewart (Daryl.Stewart@cl.cam.ac.uk)
Date: Mon Oct 15 2001 - 04:20:01 PDT
Precedence: bulk
The following reply was made to PR errata/48; it has been noted by GNATS.
From: Daryl Stewart <Daryl.Stewart@cl.cam.ac.uk>
To: Shalom.Bresticker@motorola.com
Cc: btf-bugs@boyd.com, Daryl.Stewart@cl.cam.ac.uk
Subject: Re: errata/48: Section 6.1.3 Delays (in continuous assign)
Date: Mon, 15 Oct 2001 12:10:44 +0100
Hi Shalom,
thanks for digging that one out! I recently had time to follow up on Steven's
comment about #0 delays. I'm not sure I'm happy about allowing simulation to
decide which side of a #0 an update occurs, but if this erratum is going to be
considered this late then the following is pretty non-committal about #0
schedules and doesn't contradict the golden XL model. (it says "#0 may be
used" instead of "#0 is used" and explicitly declares #0 net delay for wireB
in the example)
Please consider this version in preference to the one posted in December 2000.
cheers
Daryl
-------------
6.1.3 Delays
Values propagate through two inertial delays on their way from the right-hand
side of a continuous assignment to the left-hand side.
A delay given to a wire declaration shall specify the wire's net delay. If no
delay is given, a net delay of #0 may be used. When there is a continuous
assignment in a declaration, the delay is a driver delay for the right-hand
side specified, and no net delay is specified for the wire.
A delay given to a continuous assignment shall specify the driver delay for the
right-hand side specified.
For example:
wire #10 wireA; // specifies a net delay of 10 for wireA
wire #0 wireB; // specifies a net delay of 0 for wireB
wire #5 wireC = r1; // specifies no net delay for wireC
// and a driver delay of 5 for this assign
assign #10 wireA = r1; // specifies a driver delay of 10 for this assign
assign wireA = r2; // specifies no driver delay for this assign
assign #5 wireB = r1; // specifies a driver delay of 5 for this assign
If the left-hand side references a scalar net, then the delay shall be treated
in the same way as for gate delays - that is, different delays can be given for
the output rising, falling, and changing to high impedance (see Section 7). If
the left-hand side references a vector net, then up to three delays can be
applied. The following rules determine which delay controls the assignment:
If the right-hand side makes a transition from nonzero to zero, then the
falling delay shall be used.
If the right-hand side makes a transition to z, then the turn-off delay
shall be used.
For all other cases, the rising delay shall be used.
When a right-hand side operand of an assign changes:
a) The value of the right-hand side expression is evaluated.
b) If this right-hand side value differs from the value (if any) currently
propagating through the driver delay section for that particular assign then
the value currently propagating through the driver delay section is
descheduled.
c) If the new right-hand side value equals the value (if any) currently
propagating through the driver delay section for that particular assign then no
event is scheduled otherwise the new value is scheduled to complete the driver
delay section according to the driver delay.
Whenever a value completes propagation through the driver delay section of any
assign:
a) A new value is calculated for the wire using the new value and the last
values to propagate through all other assigns to the wire, according the
strength resolution rules.
b) If this value differs from the value (if any) currently propagating through
the net delay section for that particular wire then the value currently
propagating through the net delay section is descheduled.
c) If the new right-hand side value equals the value (if any) currently
propagating through the driver delay section for that particular assign then no
event is scheduled otherwise the new value is scheduled to complete the driver
delay section according to the driver delay.
For example in the presence of the declarations above the code:
initial r1 = 0;
initial r2 = 0;
initial begin
#100 r1 = 1;
#5 r1 = 0;
#95 r1 = 1;
#15 r1 = 0;
end // initial begin
produces the results:
r1 r2 A B C Time
----------------------------------
0 0 x x x 0
0 0 x x 0 5
0 0 x 0 0 5+#0
0 0 0 0 0 20
1 0 0 0 0 100
0 0 0 1 1 105
0 0 0 0 0 110
1 0 0 0 0 200
1 0 0 1 1 205
0 0 0 1 1 215
0 0 x 0 0 220
0 0 0 0 0 235
Notice that
a) wireC changes one #0 before wireB, since it has no net delay section.
b) the assignment of 1 to r1 at time 200 makes it through the driver delay of
#10 associated with "assign #10 wireA = r1" and although r1 changes to 0 before
the 1 reaches wireA it is not descheduled.
c) when the 1 from r1 at time 200 completes its driver delay section it is
combined with the 0 from "assign wireA = r2" to schedule a value of x at time
220.
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