From: Stuart Sutherland (stuart@sutherland-hdl.com)
Date: Wed Apr 24 2002 - 18:45:20 PDT
Precedence: bulk
Can one of you BTF gurus please respond to this?
Stu
>Sender: gvreugde@synopsys.com
>Date: Wed, 24 Apr 2002 11:56:05 -0700
>From: Gordon Vreugdenhil <gvreugde@synopsys.com>
>Reply-To: gvreugde@synopsys.com
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>To: stuart@sutherland-hdl.com
>CC: gvreugde@synopsys.com
>Subject: Verilog 2001 LRM issue
>
>Stuart,
>
>I ran into an apparent grammar/interpretation issue in the Verilog
>2001 LRM. The issue is a conflict between the grammars in Figs.
>9-1 and 9-2 versus the text at the beginning of 9.2. The grammar
>allows left hand side range selects on a memory/array in a
>procedural assign whereas the text only permits "a single word
>of a memory". The issues is whether something like:
> reg [7:0] m [9:0][9:0];
> initial m[5][5][3:0] = 0;
>would be permitted. Clearly right hand uses of such a
>select are fine.
>
>I don't know if the text is more exclusive than intended or
>whether the grammar has a "cut and paste" error from the net
>and/or expression side.
>
>If you can give me your read on this (today if at all possible)
>I would really appreciate it.
>
>Gord.
>--
>----------------------------------------------------------------------
>Gord Vreugdenhil gvreugde@synopsys.com
>Staff Engineer, VCS (Verification Tech. Group) (503) 748-3054
>Synopsys Inc., Beaverton OR
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Stuart Sutherland Sutherland HDL Inc.
stuart@sutherland-hdl.com 22805 SW 92nd Place
phone: 503-692-0898 Tualatin, OR 97062
www.sutherland-hdl.com
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