| Number | 133
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| Category | errata
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| Synopsis | Table 12: Precedence rules for operators
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| State | lrmdraft
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| Class | errata-discuss
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| Arrival-Date | Sep 26 2002
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| Originator | Shalom.Bresticker@motorola.com
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| Release | 2001b: 4.1.2
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| Environment |
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| Description |
I only have Draft 6 before me. I am looking at Table 4-4. I think it is Table 12 in the IEEE version. Please correct me if not. I looked at this following a comment by Dan Jacobi on the SystemVerilog draft, and compared this table to the corresponding SystemVerilog table. There seem to be several problems in this table. The subclause containing this table is called, "4.1.2 Binary operator precedence", and the paragraph preceding this table says, "The precedence order of binary operators and the conditional operator (?:) is shown in Table 4-4". The first problem is that unary operator precedence is not explicitly dealt with anywhere. Second, this table, despite the accompanying text, seems to contain a mixup of binary and unary operators, but incorrectly. For example, presumably unary operators should have highest precedence. Basing myself partly on the SystemVerilog draft, I propose the following changes: Change subclause name from "Binary operator precedence" to just "Operator precedence". Change the first sentence to "The precedence order of unary and binary operators and the conditional operator (?:) is shown in Table 4-4." Change the table as follows: Change top row to: Unary + - ! ~ & ~& | ~| ^ ~^ ^~ Change row 8 from: "& ~&" to "& (binary)". Change row 9 from: "^ ^~ ~^" to "^ ^~ ~^ (binary)". Change row 10 from: "| ~|" to "| (binary)". In last row (conditional operator), delete "Lowest precedence". Add new row at bottom: "{} {{}} Lowest precedence". |
| Fix |
Change subclause name FROM: "Binary operator precedence" TO : "Operator precedence". Change the first paragraph FROM: "The precedence order of binary operators and the conditional operator (?:) is shown in Table 12. The Verilog HDL has two equality operators. They are discussed in 4.1.8." TO: "The precedence order of the Verilog operators is shown in Table 12." Change Table 12 as follows: Change top row FROM: "+ - ! ~ (unary)" TO : "+ - ! ~ & ~& | ~| ^ ~^ ^~ (unary)" Change rows 8-10 FROM: & ~& ^ ^~ ~^ | ~| TO: & (binary) ^ ^~ ~^ (binary) | (binary) In last row (conditional operator), delete "Lowest precedence". Add new row at bottom: "{} {{}} Lowest precedence". REMOVE: last line of Table-10 and last line of Table-9 and Section 4.1.15 |
| Audit-Trail |
From: Shalom.Bresticker@motorola.com To: etf-bugs@boyd.com Cc: Subject: Re: errata/133: Table 12 Precedence rules for operators Date: Sun, 8 Dec 2002 15:04:27 +0200 (IST) Comment by Stu Sutherland: "The concatenation operator is listed as lowest priority, but I believe that in 1364 it is highest priority." > Add new row at bottom: "{} {{}} Lowest precedence". From: Shalom Bresticker <Shalom.Bresticker@motorola.com> To: etf-bugs@boyd.com Cc: Subject: Re: errata/133: PROPOSAL - Table 12: Precedence rules for operators Date: Wed, 29 Jan 2003 13:52:18 +0200 > REMOVE: last line of Table-10 and last line of Table-9 and Section 4.1.15 Just a note that by deleting mention of the "event or" operator from Table 10, there is no mention that "event or" is legal for use with real expressions. However, I also think that we do not need to mention it explicitly, so it is OK anyway. From: Steven Sharp <sharp@cadence.com> To: etf-bugs@boyd.com, Shalom.Bresticker@motorola.com Cc: Subject: Re: errata/133: PROPOSAL - Table 12: Precedence rules for operators Date: Wed, 29 Jan 2003 21:40:18 -0500 (EST) > Just a note that by deleting mention of the "event or" operator from Table 10, > there is no mention that "event or" is legal for use with real expressions. > > However, I also think that we do not need to mention it explicitly, so it is > OK anyway. I agree that this isn't a big deal. I just hope there aren't any other unforeseen problems with this change that might be more serious. Steven Sharp sharp@cadence.com |
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