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| Number | 189
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| Category | errata
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| Synopsis | 12.1, macromodule needs clarification
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| State | open
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| Class | enhancement
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| Arrival-Date | Nov 11 2002
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| Originator | "Brad Pierce" <Brad.Pierce@synopsys.com>
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| Release | 2001b: 12.1
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| Environment |
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| Description |
According to section 12.1 -- "The keyword macromodule can be used interchangeably with the keyword module to define a module. An implementation can choose to treat module definitions beginning with macromodule keyword differently." What does this mean? -- Brad p.s. Also, there's a missing 'the' before 'macromodule' in the second sentence. Proposal not chosen: In 12.1 -- REPLACE -- "The keyword 'macromodule' can be used interchangeably with the keyword 'module' to define a module. An implementation can choose to treat module definitions beginning with macromodule keyword differently." WITH "The keyword 'macromodule' can be used in place of the keyword 'module' to declare a module. An implementation may choose to inline the contents of modules that are declared with the 'macromodule' keyword within the modules that instantiate them. In such cases, the naming convention used to reference elements within instantiated macromodules may differ from that used to reference elements within instantiated modules." |
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| Audit-Trail |
From: Steven Sharp <sharp@cadence.com> To: etf-bugs@boyd.com, Brad.Pierce@synopsys.com Cc: Subject: Re: errata/189: 12.1, macromodule needs clarification Date: Mon, 11 Nov 2002 14:48:58 -0500 (EST) >Category: errata >Confidential: no >Originator: Steven Sharp <sharp@cadence.com> >Release: 2001b >Class: TBD >Description: Verilog-XL defined macromodules. They reduced simulation memory overhead by not creating hierarchy or scopes. They effectively got inlined where instantiated, like a macro. To allow this, they had restrictions on what could be declared inside them. I would guess that all other implementations have treated macromodules just like modules. They are still in the standard for backward compatibility reasons. Steven Sharp sharp@cadence.com From: Shalom Bresticker <Shalom.Bresticker@motorola.com> To: etf-bugs@boyd.com Cc: Subject: Re: errata/189: 12.1, macromodule needs clarification Date: Wed, 13 Nov 2002 17:28:07 +0200 >Category: errata >Confidential: no >Originator: Shalom Bresticker <Shalom.Bresticker@motorola.com> >Release: 2001b >Class: TBD >Description: Should we define restriction on what an implementation may do with them? > Verilog-XL defined macromodules. They reduced simulation memory overhead > by not creating hierarchy or scopes. They effectively got inlined where > instantiated, like a macro. To allow this, they had restrictions on what > could be declared inside them. > > I would guess that all other implementations have treated macromodules > just like modules. They are still in the standard for backward compatibility > reasons. From: Shalom Bresticker <Shalom.Bresticker@motorola.com> To: etf-bugs@boyd.com Cc: Subject: Re: errata/189: 12.1, macromodule needs clarification Date: Thu, 14 Nov 2002 13:43:48 +0200 >Category: errata >Confidential: no >Originator: Shalom Bresticker <Shalom.Bresticker@motorola.com> >Release: 2001b >Class: TBD >Description: The standard goes to the bother of explicitly mentioning macromodules in addition to modules in a few places, out of the probably hundreds of places where modules are mentioned. Since "the keyword macromodule can be used interchangeably with the keyword module to define a module," I propose we just delete mention of macromodules from all those places (except here in 12.1, in the BNF, and in 3.12, talking about namespaces). Those places are: 12.3 para. 1 13.1.1 para. 1-2 13.3.1.6 para. 4 From: "Brad Pierce" <Brad.Pierce@synopsys.com> To: <etf-bugs@boyd.com> Cc: Subject: Re: errata/189: 12.1, macromodule needs clarification Date: Fri, 15 Nov 2002 18:42:29 -0800 >Category: errata >Confidential: no >Originator: "Brad Pierce" <Brad.Pierce@synopsys.com> >Release: 2001b >Class: TBD >Description: In a recent SystemVerilog extension proposal (regarding aliases) Kevin Cameron used the "macromodule" construct in an example. So apparently it is still considered useful by some experts. So why not define it properly? At least we could add the Verilog-XL restrictions on what may be declared inside of macromodules. -- Brad From: Shalom Bresticker <Shalom.Bresticker@motorola.com> To: Brad Pierce <Brad.Pierce@synopsys.com> Cc: etf-bugs@boyd.com Subject: Re: errata/189: 12.1, macromodule needs clarification Date: Sun, 17 Nov 2002 09:13:22 +0200 >Category: errata >Confidential: no >Originator: Shalom Bresticker <Shalom.Bresticker@motorola.com> >Release: 2001b >Class: TBD >Description: > At least we could add the > Verilog-XL restrictions on what may be declared inside of > macromodules. You need to check whether those restrictions are really illegal, or whether they simply cause the macromodule to be treated as a normal module. From: Shalom.Bresticker@motorola.com To: brad.pierce@synopsys.com Cc: etf-bugs@boyd.com Subject: Re: errata/189: PROPOSAL - 12.1, macromodule needs clarification Date: Sat, 15 Feb 2003 19:38:36 +0200 (IST) It is yet more complicated than that. For example, Verilog-XL does not "inline" every macromodule, only macromodules which obey certain restrictions. Frankly, since any implementation-dependent change destroys the portability of the code, I would like better a statement whose spirit is that by default a macromodule is the same as a module, but an implementation may add a special mode which may be switched on or off which treats macromodules differently. Shalom On Tue, 11 Feb 2003 brad.pierce@synopsys.com wrote: > Date: Tue, 11 Feb 2003 19:00:23 -0800 > From: brad.pierce@synopsys.com > To: etf-bugs@boyd.com > Subject: errata/189: PROPOSAL - 12.1, macromodule needs clarification > > Precedence: bulk > > In 12.1 -- > > REPLACE -- > > "The keyword 'macromodule' can be used interchangeably with > the keyword 'module' to define a module. An implementation > can choose to treat module definitions beginning with > macromodule keyword differently." > > WITH > > "The keyword 'macromodule' can be used in place of the > keyword 'module' to declare a module. An implementation > may choose to inline the contents of modules that are > declared with the 'macromodule' keyword within the > modules that instantiate them. In such cases, the > naming convention used to reference elements within > instantiated macromodules may differ from that used > to reference elements within instantiated modules." > > > http://boydtechinc.com/cgi-bin/issueproposal.pl?cmd=view&pr=189 > From: Steven Sharp <sharp@cadence.com> To: etf-bugs@boyd.com, Shalom.Bresticker@motorola.com Cc: Subject: Re: errata/189: PROPOSAL - 12.1, macromodule needs clarification Date: Tue, 18 Feb 2003 14:58:13 -0500 (EST) Does anyone know of a tool other than Verilog-XL that treats macromodules specially? Steven Sharp sharp@cadence.com |
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