| Number | 2
|
| Category | enhancement
|
| Synopsis | Allow negative genvars
|
| State | closed
|
| Class | superceded
|
| Arrival-Date | Jul 19 2001
|
| Originator | Paul Graham, Cadence
|
| Release | 2001b: 12.1.3.1
|
| Environment |
http://boydtechinc.com/btf/archive/btf_2001/1149.html http://boydtechinc.com/btf/archive/btf_2001/1150.html |
| Description |
genvars are currently limited to non-negative values. In contrast, arrays of instances may have negative indexes. (Apparently supported by Verilog-XL, although apparently not by NC-Verilog) In VHDL, it is also allowed. Consider allowing negative values for genvars, as well. |
| Fix |
Close this issue. It is resolved by the generate proposal accepted by the VSG for issue # 113. |
| Audit-Trail |
From: Steven Sharp <sharp@cadence.com> To: etf-bugs@boyd.com Cc: Subject: Enhancement/2: negative genvars allowed Date: Tue, 6 Apr 2004 14:48:15 -0400 (EDT) The generate proposal passed by the ETF allows negative values for genvars, which would resolve this issue. Steven Sharp sharp@cadence.com Fix replaced by Shalom.Bresticker@freescale.com on Mon Jun 28 02:24:04 2004 Close this issue. It is resolved by the generate proposal accepted by the VSG for issue # 113. |
| Unformatted |
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