| Add Proposal | Add Analysis | Edit Class, Environment, or Release |
| Number | 204
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| Category | errata
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| Synopsis | 12.3.2, port definition names
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| State | open
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| Class | errata-discuss
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| Arrival-Date | Nov 20 2002
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| Originator | "Brad Pierce" <Brad.Pierce@synopsys.com>
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| Release | 2001b: 12.3.2
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| Environment |
204,227,233,234,292,332,345,452 |
| Description |
In section 12.3.2, the last sentence of the first paragraph says -- "Once a port has been defined, there shall not be another port definition with this same name." Doesn't this exclude the legal case of -- module same_name(a,a); input a; endmodule If not, what is the definition of 'port definition'? Is it merely the same thing as a port declaration? In that case, I guess the sentence is correct, since the following are all illegal -- module same_name2(input a, a); endmodule module same_name3(input a, input a); endmodule module same_name4(a,a); input a; input a; endmodule But to me the sentence does not suggest the correct idea that there is exactly one port declaration per name, but instead the incorrect idea that there is exactly one port per name. -- Brad |
| Fix |
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| Audit-Trail |
From: Shalom Bresticker <Shalom.Bresticker@motorola.com> To: etf-bugs@boyd.com Cc: Subject: Re: errata/204: 12.3.2, port definition names Date: Thu, 04 Sep 2003 11:59:28 +0300 I suggest that the following issues all be dealt with together, as they all deal with port/argument definitions and declarations: errata/204: 12.3.2, port definition names errata/227: task/function port lists and internal block item declarations errata/233: 12.3.4, nonport declarations for identifiers mentioned in list_of_port_declarations errata/234: 12.3.{2,3,6}, named port connections for implicit ports with same name errata/292: 12.3.3 : net declaration before port declaration errata/332: 12.3.3 -- port direction declarations that don't mention the size of port errata/345: 10.2.1, 10.3.1, 12.3.3, 12.3.4 -- ANSI-style port lists and redeclaration errata/452: 10.2.2, 10.3.1 -- 'reg' keyword in tf port declarations They all were submitted by the same person, by the way. -- Shalom Bresticker Shalom.Bresticker@motorola.com Design & Reuse Methodology Tel: +972 9 9522268 Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 441478 From: "James A. Markevitch" <jam@magic.com> To: etf-bugs@boyd.com Cc: Subject: Re: errata/204: 12.3.2, port definition names Date: Sun, 30 Nov 2003 17:13:38 -0800 (PST) [Re-sending this to etf-bugs, rather than etf] The comments below are intended to discuss legal syntax. Once that has been generally agreed upon, I will write the proposed changes to the text. Vendors: is the "same_name3" example below accepted by any tools? > "Once a port has been defined, there shall not be another > port definition with this same name." > > Doesn't this exclude the legal case of -- > > module same_name(a,a); > input a; > endmodule This is legal. This conforms to the Verilog 1995 syntax. > If not, what is the definition of 'port definition'? > Is it merely the same thing as a port declaration? In that case, > I guess the sentence is correct, since the following are > all illegal -- > > module same_name2(input a, a); > endmodule This is illegal. ANSI C-like declarations must be used on all ports or on no ports. > module same_name3(input a, input a); > endmodule This is illegal, but presents a problem. Presumably, the intent of the ANSI C-like declaration syntax is to eventually supplant the older style of declarations. However, if one has two ports with the same name, then there should be a way to use the ANSI C-like way to declare them. I'd like to propose that this be made legal. But, this probably falls into the category of enhancement, not erratum. Do any of the simulators accept this currently? If many of them do, then perhaps this could be justified as an erratum, rather than an enhancement. > module same_name4(a,a); > input a; > input a; > endmodule This is illegal. This was illegal in Verilog 1995 and nothing in Verilog 2001 changed that. > But to me the sentence does not suggest the correct idea that > there is exactly one port declaration per name, but instead > the incorrect idea that there is exactly one port per name. James Markevitch From: Shalom Bresticker <Shalom.Bresticker@motorola.com> To: "James A. Markevitch" <jam@magic.com> Cc: etf-bugs@boyd.com Subject: Re: errata/204: Re: errata/204: 12.3.2, port definition names Date: Mon, 01 Dec 2003 10:10:51 +0200 James, The C-like syntax is definitely more limited than the 1995 syntax. For example, in 1995 syntax, you can write module m(a[0]) ; input [0:3] a ; or module m(.a(b)) ; input b ; You cannot do these in the C-like syntax. > > module same_name3(input a, input a); > > endmodule > > This is illegal, but presents a problem. Presumably, the intent of the > ANSI C-like declaration syntax is to eventually supplant the older style > of declarations. However, if one has two ports with the same name, then > there should be a way to use the ANSI C-like way to declare them. Shalom -- Shalom Bresticker Shalom.Bresticker@motorola.com Design & Reuse Methodology Tel: +972 9 9522268 Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 441478 |
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