| Number | 259
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| Category | errata
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| Synopsis | 19.3.1: Allow escaped identifiers as text macro names
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| State | lrmdraft
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| Class | errata-simple
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| Arrival-Date | Jan 12 2003
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| Originator | Shalom.Bresticker@motorola.com
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| Release | 2001b: Syntax 19-2, A.9.3
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| Environment |
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| Description |
In 19.3.1: In Syntax 19-2 and para. 9, and in 19.4, para. 6, and in A.9.3, it says that text macro identifiers must be simple_identifiers, excluding escaped_identifiers. This is the only place in the LRM where simple identifiers are allowed and escaped identifiers are not, and I see that Verilog-XL allows escaped text macro names as well, so I propose to relax that restriction (which I foolishly added into the LRM), and allow any identifier to be a text macro name. |
| Fix |
In 19.3.1 (Syntax 19-2), and in A.9.3 CHANGE text_macro_identifier ::= simple_identifier TO text_macro_identifier ::= identifier In 19.3.1, paragraph 9, DELETE the sentence: "The text macro name shall be a simple identifier." In 19.4, paragraph 6, CHANGE the first sentence FROM: "The text_macro_identifier is a Verilog HDL simple_identifier." TO: "The text_macro_identifier is a Verilog HDL identifier." |
| Audit-Trail |
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| Unformatted |
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