| Add Proposal | Add Analysis | Edit Class, Environment, or Release |
| Number | 292
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| Category | errata
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| Synopsis | 12.3.3 : net declaration before port declaration
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| State | open
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| Class | errata-discuss
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| Arrival-Date | Mar 04 2003
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| Originator | "Brad Pierce" <Brad.Pierce@synopsys.com>
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| Release | 2001b: 12.3.3
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| Environment |
204,227,233,234,292,332,345,452 |
| Description |
Is the following example legal? module m(x); wire x; input x; endmodule -- Brad |
| Fix |
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| Audit-Trail |
From: Stephen Williams <steve@icarus.com> To: "Brad Pierce" <Brad.Pierce@synopsys.com> Cc: etf-bugs@boyd.com Subject: Re: errata/292: 12.3.3 : net declaration before port declaration Date: Tue, 04 Mar 2003 14:35:40 -0800 Brad.Pierce@synopsys.com said: > Is the following example legal? module m(x); wire x; input x; endmodule Why would it not be? Nothing in the BNF for the module contents imposes any sort of order on the module_item items, and I can find no prose that implies any sort of order. So far as I can tell, you can put the port direction declaration anywhere in the module, before or after any data type declarations for the port. The only requirement I can see is that range specifiers must match. -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, steve at picturel.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep." From: Steven Sharp <sharp@cadence.com> To: etf-bugs@boyd.com, Brad.Pierce@synopsys.com Cc: Subject: Re: errata/292: 12.3.3 : net declaration before port declaration Date: Tue, 4 Mar 2003 17:58:51 -0500 (EST) >>Number: 292 >>Category: errata >>Originator: "Brad Pierce" <Brad.Pierce@synopsys.com> >>Environment: >>Description: > >Is the following example legal? > > module m(x); > wire x; > input x; > endmodule Not according to Verilog-XL. Steven Sharp sharp@cadence.com From: "Brad Pierce" <Brad.Pierce@synopsys.com> To: <etf-bugs@boyd.com> Cc: Subject: RE: errata/292: 12.3.3 : net declaration before port declaration Date: Sat, 4 Oct 2003 11:23:21 -0700 Contrary to the claim in this thread, I get the following message from Verilog-XL 2.7 -- Error! Symbol (x) previously declared [Verilog-SSPRD] "file.v", 2: 1 error End of VERILOG-XL 2.7 Oct 4, 2003 11:03:26 for my test case module m(x); wire x; input x; endmodule I think it's a natural requirement that any declarations of the nets/variables on a port must come after the direction has been specified, e.g., module m_1(x); input wire x; endmodule or module m_2(x); input x; wire x; endmodule or module m_3(input wire x); endmodule -- Brad From: "James A. Markevitch" <jam@magic.com> To: etf-bugs@boyd.com Cc: Subject: Re: errata/292: 12.3.3 : net declaration before port declaration Date: Sun, 30 Nov 2003 18:56:39 -0800 (PST) The comments below are intended to discuss legal syntax. Once that has been generally agreed upon, I will write the proposed changes to the text. Vendors: do any existing tools support the ordering questioned in this erratum? I am inclined to consider this to be illegal. In other words, a declaration of direction must precede a net type or variable type declaration. > From: Steven Sharp <sharp@cadence.com> > To: etf-bugs@boyd.com, Brad.Pierce@synopsys.com > Cc: > Subject: Re: errata/292: 12.3.3 : net declaration before port declaration > Date: Tue, 4 Mar 2003 17:58:51 -0500 (EST) > > >>Number: 292 > >>Category: errata > >>Originator: "Brad Pierce" <Brad.Pierce@synopsys.com> > >>Environment: > >>Description: > > > >Is the following example legal? > > > > module m(x); > > wire x; > > input x; > > endmodule > > Not according to Verilog-XL. > > Steven Sharp > sharp@cadence.com How about other simulators? Do any of them support this? > From: "Brad Pierce" <Brad.Pierce@synopsys.com> > To: <etf-bugs@boyd.com> > Cc: > Subject: RE: errata/292: 12.3.3 : net declaration before port declaration > Date: Sat, 4 Oct 2003 11:23:21 -0700 > > Contrary to the claim in this thread, I get the following message > from Verilog-XL 2.7 -- > > Error! Symbol (x) previously declared [Verilog-SSPRD] > "file.v", 2: > 1 error > End of VERILOG-XL 2.7 Oct 4, 2003 11:03:26 > > for my test case > > module m(x); > wire x; > input x; > endmodule > > I think it's a natural requirement that any declarations of the > nets/variables on a port must come after the direction has been > specified, e.g., > > module m_1(x); > input wire x; > endmodule > or > module m_2(x); > input x; > wire x; > endmodule > or > module m_3(input wire x); > endmodule > > -- Brad James Markevitch From: Shalom Bresticker <Shalom.Bresticker@motorola.com> To: etf-bugs@boyd.com Cc: Subject: Re: errata/292: Re: errata/292: 12.3.3 : net declaration before port declaration Date: Mon, 01 Dec 2003 14:49:27 +0200 > > >Is the following example legal? > > > > > > module m(x); > > > wire x; > > > input x; > > > endmodule > > > > Not according to Verilog-XL. > > How about other simulators? Do any of them support this? VCS compiler does not complain. -- Shalom Bresticker Shalom.Bresticker@motorola.com Design & Reuse Methodology Tel: +972 9 9522268 Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 441478 |
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