| Add Proposal | Add Analysis | Edit Class, Environment, or Release |
| Number | 332
|
| Category | errata
|
| Synopsis | 12.3.3 -- port direction declarations that don't mention the size of port
|
| State | open
|
| Class | errata-discuss
|
| Arrival-Date | Apr 15 2003
|
| Originator | "Brad Pierce" <Brad.Pierce@synopsys.com>
|
| Release | 2001b: 12.3.3
|
| Environment |
204,227,233,234,292,332,345,452 |
| Description |
Is the following legal? -- module m (out, in) ; output out ; reg [7:0] out ; input in ; wire [7:0] in ; always @(in) out = in ; endmodule There are no examples like this in the LRM, and it seems OK to me, but it almost runs afoul of this sentence in 12.3.3 -- "If the net or variable is declared as a vector, the range specification between the two declarations of a port shall be identical." I don't know what is meant by 'between' here, but in the code example, only the reg or wire declarations include a range specification, so there's nothing to be identical with. -- Brad |
| Fix |
|
| Audit-Trail |
From: "Clifford E. Cummings" <cliffc@sunburst-design.com> To: etf-bugs@boyd.com Cc: Subject: Re: errata/332: 12.3.3 -- port direction declarations that don't mention the size of port Date: Tue, 15 Apr 2003 17:02:36 -0700 Hi, Brad - This is a Verilog-1995 style module header so both the output and reg must be declared with the same range and the input and wire (optional) must be declared with the same range. I believe the sentence is correct as is. I hate reg declarations! :-) Regards - Cliff At 04:40 PM 4/15/03 -0700, Brad Pierce wrote: >Precedence: bulk > > > >Number: 332 > >Category: errata > >Originator: "Brad Pierce" <Brad.Pierce@synopsys.com> > >Environment: > >Description: > >Is the following legal? -- > > module m (out, in) ; > > output out ; > reg [7:0] out ; > > input in ; > wire [7:0] in ; > > always @(in) out = in ; > > endmodule > >There are no examples like this in the LRM, and it seems OK to me, >but it almost runs afoul of this sentence in 12.3.3 -- > > "If the net or variable is declared as a vector, the range > specification between the two declarations of a port shall > be identical." > >I don't know what is meant by 'between' here, but in the code example, >only the reg or wire declarations include a range specification, so >there's nothing to be identical with. > >-- Brad ---------------------------------------------------- Cliff Cummings - Sunburst Design, Inc. 14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005 Phone: 503-641-8446 / FAX: 503-641-8486 cliffc@sunburst-design.com / www.sunburst-design.com Expert Verilog, Synthesis and Verification Training From: Shalom.Bresticker@motorola.com To: etf-bugs@boyd.com Cc: Subject: Re: errata/332: 12.3.3 -- port direction declarations that don't mention the size of port Date: Wed, 16 Apr 2003 06:44:59 +0300 (IDT) To clarify, at least as I understand it: The example is ILLEGAL. "output out ;" implicitly declares it as a scalar. It does "run afoul of 12.3.3". "between the two declarations" means that the same range needs to appear in both the wire/reg declaration and the port declaration. If it is unclear, then the text should be reworded. Shalom > This is a Verilog-1995 style module header so both the output and reg must > be declared with the same range and the input and wire (optional) must be > declared with the same range. I believe the sentence is correct as is. > > >Is the following legal? -- > > > > module m (out, in) ; > > > > output out ; > > reg [7:0] out ; > > > > input in ; > > wire [7:0] in ; > > > > always @(in) out = in ; > > > > endmodule > > > >There are no examples like this in the LRM, and it seems OK to me, > >but it almost runs afoul of this sentence in 12.3.3 -- > > > > "If the net or variable is declared as a vector, the range > > specification between the two declarations of a port shall > > be identical." > > > >I don't know what is meant by 'between' here, but in the code example, > >only the reg or wire declarations include a range specification, so > >there's nothing to be identical with. -- Shalom Bresticker Shalom.Bresticker@motorola.com Design & Reuse Methodology Tel: +972 9 9522268 Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 441478 From: Shalom.Bresticker@motorola.com To: etf-bugs@boyd.com Cc: Subject: Re: errata/332: 12.3.3 -- port direction declarations that don't mention the size of port Date: Wed, 16 Apr 2003 12:54:02 +0300 (IDT) Hmmm, actually I am not sure anymore. I see that Verilog-XL compiles it without an error, though I don't know whether it interprets the output port as a scalar or a vector. But then, Verilog-XL also lets you declare the output and the reg with different ranges, which is certainly against the rules. Shalom > To clarify, at least as I understand it: > > The example is ILLEGAL. > > "output out ;" implicitly declares it as a scalar. > > It does "run afoul of 12.3.3". > > "between the two declarations" means that the same range needs to appear in both > the wire/reg declaration and the port declaration. > > If it is unclear, then the text should be reworded. > > Shalom > > > > This is a Verilog-1995 style module header so both the output and reg must > > be declared with the same range and the input and wire (optional) must be > > declared with the same range. I believe the sentence is correct as is. > > > > >Is the following legal? -- > > > > > > module m (out, in) ; > > > > > > output out ; > > > reg [7:0] out ; > > > > > > input in ; > > > wire [7:0] in ; > > > > > > always @(in) out = in ; > > > > > > endmodule > > > > > >There are no examples like this in the LRM, and it seems OK to me, > > >but it almost runs afoul of this sentence in 12.3.3 -- > > > > > > "If the net or variable is declared as a vector, the range > > > specification between the two declarations of a port shall > > > be identical." > > > > > >I don't know what is meant by 'between' here, but in the code example, > > >only the reg or wire declarations include a range specification, so > > >there's nothing to be identical with. > > -- Shalom Bresticker Shalom.Bresticker@motorola.com Design & Reuse Methodology Tel: +972 9 9522268 Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 441478 From: Steven Sharp <sharp@cadence.com> To: etf-bugs@boyd.com, Brad.Pierce@synopsys.com Cc: Subject: Re: errata/332: 12.3.3 -- port direction declarations that don't mention the size of port Date: Wed, 16 Apr 2003 13:33:53 -0400 (EDT) >There are no examples like this in the LRM, and it seems OK to me, >but it almost runs afoul of this sentence in 12.3.3 -- > > "If the net or variable is declared as a vector, the range > specification between the two declarations of a port shall > be identical." > >I don't know what is meant by 'between' here, but in the code example, >only the reg or wire declarations include a range specification, so >there's nothing to be identical with. Which means it isn't identical. No range specification (which means a scalar) is clearly not an identical range specification to any actual range specification. In practice, Verilog-XL did not do strict checking. It will catch a port declared as a vector and then declared as a scalar, but not vice-versa. It will not catch mismatching ranges (apparently using the one from the reg/wire, not the port). The only time the range from the port seems to matter in XL is if there is no declaration for the reg/wire. Other tools have probably followed suit. Steven Sharp sharp@cadence.com From: Shalom.Bresticker@motorola.com To: etf-bugs@boyd.com Cc: Yair Lipa <yairl@msil.sps.mot.com> Subject: Re: errata/332: 12.3.3 -- port direction declarations that don't mention the size of port Date: Wed, 3 Sep 2003 16:42:41 +0300 (IDT) Reminder: the case was module m(in); input in ; wire [7:0] in ; endmodule Most of us seem to have agreed that it is to be considered illegal. Today I found that not only Verilog-XL accepts it, but so does VCS and NCV. All three tools also agree to consider the port as 8 bits, not as a scalar. Should we change the standard to be compatible with the tools, or remain strict ? Shalom On Wed, 16 Apr 2003, Steven Sharp wrote: > Date: Wed, 16 Apr 2003 10:40:03 -0700 > From: Steven Sharp <sharp@cadence.com> > To: etf-bugs@boyd.com > Subject: Re: errata/332: 12.3.3 -- port direction declarations that don't mention the size of port > > >There are no examples like this in the LRM, and it seems OK to me, > >but it almost runs afoul of this sentence in 12.3.3 -- > > > > "If the net or variable is declared as a vector, the range > > specification between the two declarations of a port shall > > be identical." > > > >I don't know what is meant by 'between' here, but in the code example, > >only the reg or wire declarations include a range specification, so > >there's nothing to be identical with. > > Which means it isn't identical. No range specification (which means > a scalar) is clearly not an identical range specification to any > actual range specification. > > In practice, Verilog-XL did not do strict checking. It will catch > a port declared as a vector and then declared as a scalar, but not > vice-versa. It will not catch mismatching ranges (apparently using > the one from the reg/wire, not the port). The only time the range > from the port seems to matter in XL is if there is no declaration for > the reg/wire. Other tools have probably followed suit. -- Shalom Bresticker Shalom.Bresticker@motorola.com Design & Reuse Methodology Tel: +972 9 9522268 Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 441478 From: "James A. Markevitch" <jam@magic.com> To: etf-bugs@boyd.com Cc: Subject: Re: errata/332: 12.3.3 -- port direction declarations that don't mention the size of port Date: Sun, 30 Nov 2003 19:02:45 -0800 (PST) The comments below are intended to discuss legal syntax. Once that has been generally agreed upon, I will write the proposed changes to the text. I am inclined to document this as illegal. > Is the following legal? -- > > module m (out, in) ; > > output out ; > reg [7:0] out ; > > input in ; > wire [7:0] in ; > > always @(in) out = in ; > > endmodule This appears to be illegal, although many simulators appear to accept it. The ranges must match on each of the lines. Otherwise, would the first line determine the scalarity and range? Or the last one? Or the one which has an explicit range? > There are no examples like this in the LRM, and it seems OK to me, > but it almost runs afoul of this sentence in 12.3.3 -- > > "If the net or variable is declared as a vector, the range > specification between the two declarations of a port shall > be identical." > > I don't know what is meant by 'between' here, but in the code example, > only the reg or wire declarations include a range specification, so > there's nothing to be identical with. > > -- Brad James Markevitch From: Shalom Bresticker <Shalom.Bresticker@motorola.com> To: etf-bugs@boyd.com Cc: Subject: Re: errata/332: Re: errata/332: 12.3.3 -- port direction declarations that don't mention the size of port Date: Mon, 01 Dec 2003 15:04:01 +0200 > > "If the net or variable is declared as a vector, the range > > specification between the two declarations of a port shall > > be identical." The previous sentence says, "If a port declaration does not include a net or variable type, then the port can be again declared in a net or variable declaration." If we decide to require that both declarations of a vector port require range specifications, then I would reword the sentence "If the net or variable is declared as a vector, the range specification between the two declarations of a port shall be identical." to be "If either declaration contains a range specification, then the other declaration shall contain an identical range specification as well." -- Shalom Bresticker Shalom.Bresticker@motorola.com Design & Reuse Methodology Tel: +972 9 9522268 Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 441478 |
| Unformatted |
|
Hosted by Boyd Technology