ISSUE 34

Number 34
Category errata
Synopsis 17.2.3: "Formatting data to a string"
State lrmdraft
Class errata-simple
Arrival-DateSep 06 2001
Originator Daryl Stewart
Release 2001b: 17.2.3
Environment
Issue #41
Description
Syntax 17-6 (p299) contains the following typo:

non-terminal string_output_tasks makes
use of non-terminal string_output_tasks_name

string_output_tasks_name is NOT defined
string_output_task_name is defined instead

Suggest changing string_output_tasks_name to string_output_task_name,
as other similar syntaxes use the singular form.

Also

The definition of variable_format_string_output_task mentions a "format".
This is called a "format_string" everywhere else.

Also

p299 contains a paragraph beginning
"The syntax for the string output system tasks is..." which
(1) is redundant wrt the table "Syntax 17-6" *immediately* above it
(2) shows the assignment of a $sformat system TASK to "length": length
is never referenced and the use of a TASK in an assignment is not
explained.
Fix
A. In 17.2.3, in Syntax 17-6, in the first production, change

"string_output_tasks_name"

to

"string_output_task_name"

**

B. In the last line of Syntax 17-6, CHANGE

$sformat (output_reg ,format ,list_of_arguments );

TO

$sformat (output_reg ,format_string ,list_of_arguments );

**

C. Following Syntax 17-6, DELETE the following lines:

"The syntax for the string output system tasks is

$swrite (output_reg , list_of_arguments );
$sformat (output_reg , format_string , list_of_arguments );
length = $sformat (output_reg , format_string , list_of_arguments );"

**

D. Delete the following paragraph (which appears two
paragraphs after the preceding), as it also appears at the
end of 17.2.3:

"The variable output_reg is assigned using the Verilog's
string assignment to variable rules,as specified in 4.2.3."

**

E. CHANGE the last paragraph of 17.2.3 FROM

"The variable output_reg is assigned using the Verilog's
string assignment to variable rules, as specified in 4.2.3."

TO

"The variable output_reg is assigned using the
string assignment to variable rules, as specified in 4.2.3."

Audit-Trail

From: Shalom Bresticker <Shalom.Bresticker@motorola.com>
To: btf-bugs@boyd.com
Cc: Daryl.Stewart@cl.cam.ac.uk
Subject: Re: errata/34: Section 17.2.3 "Formatting data to a string"
Date: Thu, 11 Oct 2001 16:49:29 +0200

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I just noticed that the last part of this errata is the same as errata/41.

Since the rest of errata/34 is editorial errors and this is a technical content error,
I would prefer to keep them separate.

Shalom


Daryl.Stewart@cl.cam.ac.uk wrote:

> p299 contains a paragraph beginning
> "The syntax for the string output system tasks is..." which
>
> (2) shows the assignment of a $sformat system TASK to "length": length
> is never referenced and the use of a TASK in an assignment is not
> explained.

--
**************************************************************************
Shalom Bresticker Shalom.Bresticker@motorola.com
Motorola Semiconductor Israel, Ltd. Tel #: +972 9 9522268
P.O.B. 2208, Herzlia 46120, ISRAEL Fax #: +972 9 9522890
**************************************************************************



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I just noticed that the last part of this errata is the same as errata/41.

Since the rest of errata/34 is editorial errors and this is a technical
content error,

I would prefer to keep them separate.

Shalom

 

Daryl.Stewart@cl.cam.ac.uk wrote:
<blockquote TYPE=CITE>p299 contains a paragraph beginning

"The syntax for the string output system tasks is..." which

(2) shows the assignment of a $sformat system TASK to "length": length

is never referenced and the use of a TASK in an assignment is not

explained. 

-- 
 **************************************************************************
 Shalom Bresticker                           Shalom.Bresticker@motorola.com
 Motorola Semiconductor Israel, Ltd.                  Tel #: +972 9 9522268
 P.O.B. 2208, Herzlia 46120, ISRAEL                   Fax #: +972 9 9522890
 **************************************************************************

 

--------------7BA288D7AF7464C9D562391B--


From: Karen Pieper <Karen.Pieper@synopsys.com>
To: etf-bugs@boyd.com
Cc:
Subject: Re: errata/34: Section 17.2.3 "Formatting data to a string"
Date: Fri, 04 Oct 2002 16:14:33 -0700

>Category: errata
>Confidential: no
>Originator: Karen Pieper <Karen.Pieper@synopsys.com>
>Class: TBD
>Description:
Proposed wording:

In Syntax box 17-6:
Original wording: "string_output_tasks_name"
New wording: "string_output_task_name"

Original wording: "output_reg, format, list_of_arguments"
New wording: "output_reg, format_string, list_of_arguments"

In Section 17.2.3
Delete the sentence reading "The syntax for the string output system tasks is

$swrite(output_reg, list_of_arguments);
$sformat(output_reg, format_string, list_of_arguments);
length = $sformat(output_reg, format_string, list_of_arguments);"



Karen


From: "Brad Pierce" <Brad.Pierce@synopsys.com>
To: <etf-bugs@boyd.com>
Cc:
Subject: Re: errata/34: Section 17.2.3 "Formatting data to a string"
Date: Mon, 7 Oct 2002 11:23:17 -0700

>Category: errata
>Confidential: no
>Originator: "Brad Pierce" <Brad.Pierce@synopsys.com>
>Release: 2001b
>Class: TBD
>Description:
This is a multi-part message in MIME format.

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charset="iso-8859-1"
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In the last paragraph of p. 289, "using the Verilog s string" should be
"using the Verilog string", that is, "s" should be deleted.

-- Brad



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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">

<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Diso-8859-1">
<META content=3D"MSHTML 5.50.4807.2300" name=3DGENERATOR>

<FONT face=3DArial size=3D2><SPAN class=3D577421818-07102002>In the =
last=20
paragraph of p. 289, "using the Verilog s string" should be "using the =
Verilog=20
string", that is, "s" should be deleted.

<FONT face=3DArial size=3D2><SPAN=20
class=3D577421818-07102002> 

<FONT face=3DArial size=3D2><SPAN class=3D577421818-07102002>--=20
Brad

<FONT face=3DArial size=3D2><SPAN=20
class=3D577421818-07102002> 

<FONT face=3DArial size=3D2><SPAN=20
class=3D577421818-07102002> 


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From: Shalom Bresticker <Shalom.Bresticker@motorola.com>
To: etf-bugs@boyd.com
Cc:
Subject: Re: errata/34: Section 17.2.3 "Formatting data to a string"
Date: Tue, 08 Oct 2002 08:25:55 +0200

>Category: errata
>Confidential: no
>Originator: Shalom Bresticker <Shalom.Bresticker@motorola.com>
>Release: 2001b
>Class: TBD
>Description:
> In the last paragraph of p. 289, "using the Verilog s string" should be
> "using the Verilog string", that is, "s" should be deleted.

That should have been "Verilog's", with an apostrophe before the s.
An IEEE problem caused many apostrophes in the document not to appear.
That is a separate erratum (which I still have to file, along with all the
other
formatting problems we know about).


From: "Brad Pierce" <Brad.Pierce@synopsys.com>
To: <etf-bugs@boyd.com>
Cc:
Subject: Re: errata/34: Section 17.2.3 "Formatting data to a string"
Date: Tue, 8 Oct 2002 09:19:03 -0700

>Category: errata
>Confidential: no
>Originator: "Brad Pierce" <Brad.Pierce@synopsys.com>
>Release: 2001b
>Class: TBD
>Description:

Even with an apostrophe the sentence doesn't make sense, because of the
superfluous 'the' before 'Verilog'. Could we shorten this sentence to

"The variable output_reg is assigned using the rules specified
in 4.2.3."

?

-- Brad



From: Shalom.Bresticker@motorola.com
To: Brad Pierce <Brad.Pierce@synopsys.com>
Cc: etf-bugs@boyd.com
Subject: Re: errata/34: Section 17.2.3 "Formatting data to a string"
Date: Wed, 9 Oct 2002 04:36:35 +0200 (IST)

>Category: errata
>Confidential: no
>Originator: Shalom.Bresticker@motorola.com
>Release: 2001b
>Class: TBD
>Description:
From a strict English point of view, I think it is still OK as is,
but I agree that the words "the Verilog's" are superfluous.

I don't think it is a true erratum, though. Just a small language improvement.

I would just delete the words "the Verilog's", however, and leave the part about
the "string assignment to variable".

Shalom

On Tue, 8 Oct 2002, Brad Pierce wrote:

> Even with an apostrophe the sentence doesn't make sense, because of the
> superfluous 'the' before 'Verilog'. Could we shorten this sentence to
>
> "The variable output_reg is assigned using the rules specified
> in 4.2.3."


Unformatted


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