| Number | 340
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| Category | errata
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| Synopsis | /210
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| State | closed
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| Class | mistaken
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| Arrival-Date | May 05 2003
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| Originator | "James A. Markevitch" <jam@magic.com>
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| Release | 2001b
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| Environment |
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| Description |
Proposal: reject the comment Although it might have made sense to allow anonymous module instantiation when Verilog was a new language, at this point the impact of making such a change is probably substantial. As has been pointed out from the e-mail thread on this topic, instance names for instantiated modules are valuable in their use of examining the hierarchy below that instantiation. Adding the notion of anonymous module instantiation would result in: loss of the ability to inspect the contents of such an instatiation; and/or, loss of PLI access to such a module; and/or the requirement to specify how such access could be restored. James Markevitch |
| Fix |
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| Audit-Trail |
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| Unformatted |
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