| Number | 345
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| Category | errata
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| Synopsis | 10.2.1, 10.3.1, 12.3.3, 12.3.4 -- ANSI-style port lists and redeclaration
|
| State | closed
|
| Class | duplicate
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| Arrival-Date | May 09 2003
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| Originator | "Brad Pierce" <Brad.Pierce@synopsys.com>
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| Release | 2001b: 10.2.1, 10.3.1, 12.3.3, 12.3.4
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| Environment |
204,227,233,234,292,332,345,452 |
| Description |
According to 12.3.4, regarding ANSI-style module ports, "Each declared port provides the complete information about the port." According to 12.3.3, if a port declaration does not include a net or variable type, then the port can be again declared in a net or variable declaration." Does this mean that the following is legal? -- module m( input x ) ; wire x ; endmodule I think it shouldn't be. If the information is complete, then even redundant declarations should be prohibited. Are there any restrictions on redeclarations of ANSI-style task/function ports? I don't see any restrictions in 10.2.1 and 10.3.1. To me it would make sense if each ANSI-style task/function declaration would provide the complete information about the port and if it would be illegal to redeclare such ports within the body, even redundantly. -- Brad |
| Fix |
closed as duplicate of 227 and 233, similar issues are discussed in 292 and 332 |
| Audit-Trail |
From: Shalom Bresticker <Shalom.Bresticker@motorola.com> To: Brad Pierce <Brad.Pierce@synopsys.com> Cc: etf-bugs@boyd.com Subject: Re: errata/345: 10.2.1, 10.3.1, 12.3.3, 12.3.4 -- ANSI-style port lists and redeclaration Date: Wed, 28 May 2003 18:15:13 +0300 I believe this duplicates issues 227 and 233. Also, similar issues are discussed in 292 and 332. Shalom Brad Pierce wrote: > According to 12.3.4, regarding ANSI-style module ports, "Each declared > port provides the complete information about the port." According to > 12.3.3, if a port declaration does not include a net or variable type, > then the port can be again declared in a net or variable declaration." > > Does this mean that the following is legal? -- > > module m( input x ) ; > wire x ; > endmodule > > I think it shouldn't be. If the information is complete, then even > redundant declarations should be prohibited. > > Are there any restrictions on redeclarations of ANSI-style > task/function ports? I don't see any restrictions in 10.2.1 and > 10.3.1. To me it would make sense if each ANSI-style task/function > declaration would provide the complete information about the port > and if it would be illegal to redeclare such ports within the body, > even redundantly. -- Shalom Bresticker Shalom.Bresticker@motorola.com Design & Reuse Methodology Tel: +972 9 9522268 Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 441478 From: "James A. Markevitch" <jam@magic.com> To: etf-bugs@boyd.com Cc: Subject: Re: errata/345: 10.2.1, 10.3.1, 12.3.3, 12.3.4 -- ANSI-style port lists and redeclaration Date: Sun, 30 Nov 2003 19:55:42 -0800 (PST) The comments below are intended to discuss legal syntax. Once that has been generally agreed upon, I will write the proposed changes to the text. > According to 12.3.4, regarding ANSI-style module ports, "Each declared > port provides the complete information about the port." According to > 12.3.3, if a port declaration does not include a net or variable type, > then the port can be again declared in a net or variable declaration." > > Does this mean that the following is legal? -- > > module m( input x ) ; > wire x ; > endmodule Illegal. An ANSI C-style declaration is complete and nothing should attempt to augment it. > I think it shouldn't be. If the information is complete, then even > redundant declarations should be prohibited. > > Are there any restrictions on redeclarations of ANSI-style > task/function ports? I don't see any restrictions in 10.2.1 and > 10.3.1. To me it would make sense if each ANSI-style task/function > declaration would provide the complete information about the port > and if it would be illegal to redeclare such ports within the body, > even redundantly. These declarations are the same as for modules. They should be complete and it is illegal to redeclare them. > -- Brad James Markevitch From: Shalom.Bresticker@motorola.com To: stefen@boyd.com Cc: etf-bugs@boyd.com Subject: Re: errata/345: 10.2.1, 10.3.1, 12.3.3, 12.3.4 -- ANSI-style port lists and redeclaration Date: Sun, 22 Feb 2004 13:15:47 +0200 (IST) Stefen, Please close this issue as a duplicate, as decided by the ETF in the last meeting. Thanks, Shalom On Wed, 28 May 2003, Shalom Bresticker wrote: > I believe this duplicates issues 227 and 233. > Also, similar issues are discussed in 292 and 332. > > Shalom > > > Brad Pierce wrote: > > > According to 12.3.4, regarding ANSI-style module ports, "Each declared > > port provides the complete information about the port." According to > > 12.3.3, if a port declaration does not include a net or variable type, > > then the port can be again declared in a net or variable declaration." > > > > Does this mean that the following is legal? -- > > > > module m( input x ) ; > > wire x ; > > endmodule > > > > I think it shouldn't be. If the information is complete, then even > > redundant declarations should be prohibited. > > > > Are there any restrictions on redeclarations of ANSI-style > > task/function ports? I don't see any restrictions in 10.2.1 and > > 10.3.1. To me it would make sense if each ANSI-style task/function > > declaration would provide the complete information about the port > > and if it would be illegal to redeclare such ports within the body, > > even redundantly. -- Shalom Bresticker Shalom.Bresticker@motorola.com Design & Reuse Methodology Tel: +972 9 9522268 Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 441478 [x]Motorola General Business Information [ ]Motorola Internal Use Only [ ]Motorola Confidential Proprietary |
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