| Add Proposal | Add Analysis | Edit Class, Environment, or Release |
| Number | 360
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| Category | errata
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| Synopsis | D.3-D.6: delay modes not defined
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| State | open
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| Class | errata-discuss
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| Arrival-Date | Jun 08 2003
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| Originator | Shalom.Bresticker@motorola.com
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| Release | 2001b:D.3-D.6
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| Environment |
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| Description |
Sections D.3-D.6 describe optional compiler directives for specifying delay modes. D.3 is `delay_mode_distributed D.4 is `delay_mode_path D.5 is `delay_mode_unit D.6 is `delay_mode_zero These modes are not sufficiently defined in these sections. The Cadence Verilog-XL User Guide may contain fuller descriptions of these modes. |
| Fix |
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| Audit-Trail |
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| Unformatted |
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