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| Number | 364
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| Category | errata
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| Synopsis | 19.3: Preprocessor macros within strings
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| State | open
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| Class | errata-discuss
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| Arrival-Date | Jun 15 2003
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| Originator | Stephen Williams <steve@icarus.com>
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| Release | 2001b: 19.3
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| Description |
I'm searching in the IEEE1364-2001 for the statement or string of statements that says that preprocessor macros cannot appear in strings. I'm not finding such a thing. Here's an example: module main; `define HI Hello initial $display("`HI, world."); endmodule Should I expect to print: `HI, world Or should substitution be done, to get: Hello, world. The standard says "The text specified for macro text shall not be split across the following lexical tokens: ..." and includes strings. But macro text can clearly be a complete string, number, whatever. I believe the intent is that macro substitution *not* happen within lexical strings. Otherwise, absurdities can occur. This should be said explicitly. Perhaps this note can be added: NOTE: Strings are lexical units, so macros are not expanded or recognized within quoted strings. For example, "`HI, world" is not scanned for directives or macros. -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep." |
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| Audit-Trail |
From: Stephen Williams <steve@icarus.com> To: Cc: etf-bugs@boyd.com Subject: Re: errata/364: Preprocessor macros within strings. Date: Sun, 15 Jun 2003 17:30:42 -0700 module main; `define HI Hello initial $display("`HI, world."); endmodule Actually, here I am following up to my own errata report. It appears that at least one compiler in the wild (besides Icarus Verilog) does indeed do macro substitution within strings. <http://www.icarus.com/cgi-bin/ivl-bugs?findid=622> This suggests that I'm not losing it completely, and perhaps macro substitution within strings is legal. That's tricky business. To wit: `define foo "Hello" initial $display("`foo makes a mess"); One might simply call this a You-get-what-you-deserve type of coding error, given my original observation that it is not explicitly prohibited, and in this case macro expansion within strings should be explicitly allowed within strings. NOTE: Macros are substituted within lexical strings. A macro value that contains double-quote characters may therefore cause an error if it is itself (or if it contains) a quoted string, as the double-quotes within the macro would interfere with the lexical string itself. Personally, I prefer not allowing macro substitution within strings. -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep." From: Michael McNamara <mac@verisity.com> To: Stephen Williams <steve@icarus.com> Cc: etf-bugs@boyd.com Subject: Re: errata/364: Preprocessor macros within strings. Date: Mon, 16 Jun 2003 16:37:29 -0700 Macros have always been substituted in strings in Verilog, since time began (I'm looking at a Verilog-XL 1.1a manual (March 1987), where this is documented on page 2-6). Stephen Williams writes: > Precedence: bulk > > The following reply was made to PR errata/364; it has been noted by GNATS. > > From: Stephen Williams <steve@icarus.com> > To: Cc: etf-bugs@boyd.com > Subject: Re: errata/364: Preprocessor macros within strings. > Date: Sun, 15 Jun 2003 17:30:42 -0700 > > module main; > `define HI Hello > initial $display("`HI, world."); > endmodule > > Actually, here I am following up to my own errata report. It appears > that at least one compiler in the wild (besides Icarus Verilog) does > indeed do macro substitution within strings. > > <http://www.icarus.com/cgi-bin/ivl-bugs?findid=622> > > This suggests that I'm not losing it completely, and perhaps macro > substitution within strings is legal. That's tricky business. To wit: > > `define foo "Hello" > initial $display("`foo makes a mess"); > > One might simply call this a You-get-what-you-deserve type of coding > error, given my original observation that it is not explicitly > prohibited, and in this case macro expansion within strings should > be explicitly allowed within strings. > > NOTE: Macros are substituted within lexical strings. A macro > value that contains double-quote characters may therefore cause > an error if it is itself (or if it contains) a quoted string, > as the double-quotes within the macro would interfere with the > lexical string itself. > > Personally, I prefer not allowing macro substitution within strings. > > -- > Steve Williams "The woods are lovely, dark and deep. > steve at icarus.com But I have promises to keep, > http://www.icarus.com and lines to code before I sleep, > http://www.picturel.com And lines to code before I sleep." > > From: Stephen Williams <steve@icarus.com> To: mac@verisity.com Cc: etf-bugs@boyd.com Subject: Re: errata/364: Preprocessor macros within strings. Date: Mon, 16 Jun 2003 09:35:02 -0700 mac@verisity.com said: > Macros have always been substituted in strings in Verilog, since time > began (I'm looking at a Verilog-XL 1.1a manual (March 1987), where > this is documented on page 2-6). That may be so, but I'm going by the written standard which is slightly vague on this matter. I don't have access to the expensive tools for comparison purposes, nor should the standard be left to lore, word-of-mouth and bug-compatibility. Anyhow, I'm just trying to make it language-lawyer clear. The current wording managed to confuse this C programmer twice. -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep." From: Shalom Bresticker <Shalom.Bresticker@motorola.com> To: Michael McNamara <mac@verisity.com> Cc: etf-bugs@boyd.com Subject: Re: errata/364: Preprocessor macros within strings. Date: Mon, 16 Jun 2003 19:38:26 +0300 Michael McNamara wrote: > Macros have always been substituted in strings in Verilog, since time > began (I'm looking at a Verilog-XL 1.1a manual (March 1987), where > this is documented on page 2-6). Such a statement does not appear in the Verilog-XL 5.0 manual, nor does it simulate that way in VXL 4.0: `define QQ aaaa module qq; initial $display(" `QQ "); endmodule The result is: -- Shalom Bresticker Shalom.Bresticker@motorola.com Design & Reuse Methodology Tel: +972 9 9522268 Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 441478 From: Shalom Bresticker <Shalom.Bresticker@motorola.com> To: Stephen Williams <steve@icarus.com> Cc: etf-bugs@boyd.com Subject: Re: errata/364: Preprocessor macros within strings. Date: Mon, 16 Jun 2003 19:48:57 +0300 > The standard says "The text specified for macro text shall not be > split across the following lexical tokens: ..." and includes strings. > But macro text can clearly be a complete string, number, whatever. So I have interpreted that statement to mean that just as you can not write an identifier name as: aa`BBBcc (although we would like to be able to do so) then you can also not write "aa `BBB cc" -- Shalom Bresticker Shalom.Bresticker@motorola.com Design & Reuse Methodology Tel: +972 9 9522268 Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 441478 From: Steven Sharp <sharp@cadence.com> To: etf-bugs@boyd.com, mac@verisity.com Cc: Subject: Re: errata/364: Preprocessor macros within strings. Date: Mon, 16 Jun 2003 18:40:13 -0400 (EDT) > Macros have always been substituted in strings in Verilog, since time > began (I'm looking at a Verilog-XL 1.1a manual (March 1987), where > this is documented on page 2-6). Mac, can you quote the text you are referring to from the 1.1a manual? The earliest I have is a 1.6c manual from June 1993, which doesn't say anything about it. The OVI 2.0 LRM from March 1993 also doesn't say anything about it. At any rate, a current version of Verilog-XL does not substitute macros in strings. This might be a situation where Verilog has evolved since time began. Steven Sharp sharp@cadence.com |
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