| Number | 39
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| Category | errata
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| Synopsis | 12.3.3 describes wrong tied connections
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| State | lrmdraft
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| Class | errata-simple
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| Arrival-Date | Oct 07 2001
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| Originator | Shalom.Bresticker@motorola.com
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| Release | 2001a: 12.3.3
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| Environment |
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| Description |
Date: Mon, 12 Mar 2001 11:30:47 +0200 From: "Shalom Bresticker (r50386)" <r50386@email.sps.mot.com> I just noticed that the following error was not fixed in sectino 12.3.3 (as of Draft 6, which is what I have). To quote Steven Sharp: "Shalom is correct. To be consistent with everything else about port connections, the input nets should be "tied together", not "ored". If the ports get collapsed (as most ports do), there is no way they could be "ored". The same applies if the ports were declared as outputs or inouts. If this goes in, it will be a new error, not a clarification." Shalom -------- Original Message -------- Subject: Re: Minutes from today's VSG call Date: Sun, 13 Feb 2000 14:30:58 +0200 From: Shalom Bresticker <shalom@msil.sps.mot.com> Lynn Horobin wrote: IEEE 1364 Verilog Standards Group Teleconference Minutes February 11, 2000 D) Port restrictions clarification - e-mail from Anders Nordstrom - 2/10/00 (Subject: BTF - VSG Vote on Friday: Port declaration errata) Motion: Define the behaviour in two previously undocumented cases of port declarations. Draft 4 page 186 just above section 12.3.7, Add the following text: Multiple module instance port connections are not allowed i.e. the following example is illegal: Example: module test; a ia (.i (a), .i (b), // illegal connection of input port twice. .o (c), .o (d), // illegal connection of output port twice. .e (e), .e (f)); // illegal connection of inout port twice. endmodule Proposed: Cliff Cummings Seconded: Stefen Boyd Motion passed unanimously. Add the following text after the last example. Draft 4 page 184 just above section 12.3.4 module same_input (a,a); //This is legal. The inputs are ored input a; // together. Proposed: Cliff Cummings Seconded: Stefen Boyd Motion passed unanimously. This is not logical. It means that if one port is connected to 0 and the other port to 1, the 1 takes precedence. That's the meaning of "or". It should be a multiple continous assignment, as described in 5.6.6. If it is connected to 0 and 1, the result is X (assuming equal strength). If one is stronger than the other, the stronger one takes precedence. |
| Fix |
Sent to IEEE in October 2001: Passed 10/7/02: Change last line of example in 12.3.3: REPLACE: input a; // This is legal. The inputs are ored together. WITH: input a; // This is legal. The inputs are tied together. |
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