| Number | 425
|
| Category | errata
|
| Synopsis | "macromodule" use
|
| State | lrmdraft
|
| Class | errata-discuss
|
| Arrival-Date | Aug 21 2003
|
| Originator | Shalom Bresticker <Shalom.Bresticker@motorola.com>
|
| Release | 2001c: 3.12, 12.3, 13.1.1, 13.3.1.6
|
| Environment |
|
| Description |
Following the submission of the previous issue, and noting that the phrase "module or macromodule" etc. is frequently used, I propose that we write that the term "module" refers to a macromodule as well (which is actually more or less already stated), unless specifically excluded, and then we can probably delete 90% of the references to macromodules. Of course, we have to check that the cure is not worse than the disease... -- Shalom Bresticker Shalom.Bresticker@motorola.com Design & Reuse Methodology Tel: +972 9 9522268 Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 441478 |
| Fix |
It is inconsistent to mention macromodules sometimes in addition to modules, but not always. It gives the impression that where they are not mentioned, there is a difference. It also encourages their use and simply makes the text more verbose and lengthier. Note also that they are nowhere mentioned in the PLI. I propose to delete mention of macromodule everywhere except in 12.1 para. 3: "The keyword macromodule can be used interchangeably with the keyword module to define a module. An implementation may choose to treat module definitions beginning with the macromodule keyword differently." and in Syntax 12-1 and A.1.3: module_keyword ::= module | macromodule and in the list of keywords in Annex B. Specifically, I propose to delete the mention of macromodules from the following places: 3.12 Namespaces, para. 1 (in 3 places): "In Verilog HDL, there are seven name spaces; two are global and five are local. The global name spaces are definitions and text macros. The definitions name space unifies all the module (see 12.1), macromodule (see 12.1), and primitive (see 8.1) definitions. Once a name is used to define a module, macromodule, or primitive, the name shall not be used again to declare another module, macromodule, or primitive." para. 5: "The module name space is introduced by the module, macromodule, and primitive constructs. It unifies the definition of functions, tasks, named blocks, instance names, parameters, named events, net type of declaration, and variable type of declaration. The net type of declaration includes wire, wor, wand, tri, trior, triand, tri0, tri1, trireg, supply0, and supply1 (see 3.7)." para. 6: "The port name space is introduced by the module, macromodule, primitive, function, and task constructs. It provides a means of structurally defining connections between two objects that are in two different name spaces. The connection can be unidirectional (either input or output) or bidirectional (inout). The port name space overlaps the module and the block name spaces. Essentially, the port name space specifies the type of connection between names in different name spaces. The port type of declarations include input, output, and inout (see 12.3). A port name introduced in the port name space can be reintroduced in the module name space by declaring a variable or a wire with the same name as the port name." 12.3 Ports: "Ports provide a means of interconnecting a hardware description consisting of modules, primitives, and macromodules. For example, module A can instantiate module B, using port connections appropriate to module A. These port names can differ from the names of the internal nets and variables specified in the definition of module B." 13.1.1 Library notation, para. 1 (in 2 places) and para. 2: "In order to map a Verilog instance to a source description, the concept of a symbolic library, which is simply a logical collection of design elements (such as modules, macromodules, primitives, or configs) can be used. These design elements can be referred to as cells. The cell name shall be the same as the name of the module/macromodule/primitive/config being processed. Syntax 13-1 specifies a cell from a given library. This notation gives a symbolic method of referring to source descriptions; the method of mapping source descriptions into libraries is shown in greater detail in 13.2.1. The optional :config extension shall be used explicitly to refer to a config in the case where a config has the same name as a module/macromodule/primitive." 13.3.1.6 The use clause, para. 4: "If the lib.cell being referred to by the use clause is a config which has the same name as a module/macromodule/primitive in the same library, then the optional :config suffix can be added to the lib.cell to specify the config explicitly." |
| Audit-Trail |
Fix replaced by Shalom.Bresticker@freescale.com on Tue Jun 29 02:45:59 2004 It is inconsistent to mention macromodules sometimes in addition to modules, but not always. It gives the impression that where they are not mentioned, there is a difference. It also encourages their use and simply makes the text more verbose and lengthier. Note also that they are nowhere mentioned in the PLI. I propose to delete mention of macromodule everywhere except in 12.1 para. 3: "The keyword macromodule can be used interchangeably with the keyword module to define a module. An implementation may choose to treat module definitions beginning with the macromodule keyword differently." and in Syntax 12-1 and A.1.3: module_keyword ::= module | macromodule and in the list of keywords in Annex B. Specifically, I propose to delete the mention of macromodules from the following places: 3.12 Namespaces, para. 1 (in 3 places): "In Verilog HDL, there are seven name spaces; two are global and five are local. The global name spaces are definitions and text macros. The definitions name space unifies all the module (see 12.1), macromodule (see 12.1), and primitive (see 8.1) definitions. Once a name is used to define a module, macromodule, or primitive, the name shall not be used again to declare another module, macromodule, or primitive." para. 5: "The module name space is introduced by the module, macromodule, and primitive constructs. It unifies the definition of functions, tasks, named blocks, instance names, parameters, named events, net type of declaration, and variable type of declaration. The net type of declaration includes wire, wor, wand, tri, trior, triand, tri0, tri1, trireg, supply0, and supply1 (see 3.7)." para. 6: "The port name space is introduced by the module, macromodule, primitive, function, and task constructs. It provides a means of structurally defining connections between two objects that are in two different name spaces. The connection can be unidirectional (either input or output) or bidirectional (inout). The port name space overlaps the module and the block name spaces. Essentially, the port name space specifies the type of connection between names in different name spaces. The port type of declarations include input, output, and inout (see 12.3). A port name introduced in the port name space can be reintroduced in the module name space by declaring a variable or a wire with the same name as the port name." 12.3 Ports: "Ports provide a means of interconnecting a hardware description consisting of modules, primitives, and macromodules. For example, module A can instantiate module B, using port connections appropriate to module A. These port names can differ from the names of the internal nets and variables specified in the definition of module B." 13.1.1 Library notation, para. 1 (in 2 places) and para. 2: "In order to map a Verilog instance to a source description, the concept of a symbolic library, which is simply a logical collection of design elements (such as modules, macromodules, primitives, or configs) can be used. These design elements can be referred to as cells. The cell name shall be the same as the name of the module/macromodule/primitive/config being processed. Syntax 13-1 specifies a cell from a given library. This notation gives a symbolic method of referring to source descriptions; the method of mapping source descriptions into libraries is shown in greater detail in 13.2.1. The optional :config extension shall be used explicitly to refer to a config in the case where a config has the same name as a module/macromodule/primitive." 13.3.1.6 The use clause, para. 4: "If the lib.cell being referred to by the use clause is a config which has the same name as a module/macromodule/primitive in the same library, then the optional :config suffix can be added to the lib.cell to specify the config explicitly." |
| Unformatted |
|
Hosted by Boyd Technology