| Number | 437
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| Category | enhancement
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| Synopsis | A proposal for adding verification test bench specific enhancements
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| State | closed
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| Class | duplicate
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| Arrival-Date | Aug 23 2003
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| Originator | Ennis Hawk, Jeda Technologies
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| Release | 2005
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| Environment |
duplicates 455 |
| Description |
A proposal on extending Verilog to add the verification layer that contains commands and constructs to be used for writting test benches for verification of hardware designs. It includes object-oriented programming support for writing modular and reusable test benches, procedural code execution with dynamic concurrent programming support, various synchronization/mutex primitives for multi-threaded execution, cycle based test bench construction support, enhanced list and array data types for high level behavior modeling, and aspect-oriented programming support. |
| Fix |
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| Audit-Trail |
From: Shalom Bresticker <Shalom.Bresticker@motorola.com> To: stefen@boyd.com Cc: btf-bugs@boyd.com Subject: enhancement/437: please close this issue, it duplicates 455 Date: Wed, 01 Oct 2003 09:56:23 +0300 -- Shalom Bresticker Shalom.Bresticker@motorola.com Design & Reuse Methodology Tel: +972 9 9522268 Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 441478 State-Changed-From-To: open->closed State-Changed-By: stefen@wa.boyd.com State-Changed-When: Sat, 04 Oct 2003 04:28:33 -0700 State-Changed-Why: |
| Unformatted |
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