| Add Proposal | Add Analysis | Edit Class, Environment, or Release |
| Number | 443
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| Category | enhancement
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| Synopsis | Allow modules to be passed through ports
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| State | open
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| Class | enhancement
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| Arrival-Date | Aug 25 2003
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| Originator | Jay Lawrence - Cadence Design Systems
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| Release | 2001b
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| Environment |
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| Description |
This enhancement request proposes that modules be allowed to be passed hierarchical up or down through port lists. This behavior would similar to the functionality of SystemC channels and SystemVerilog interfaces. An example of passing a module down the hierarchy would be as follows: module bus #(integer num_periph) // maximum number of devices on bus (input wire clk); // input system clock reg [num_periph-1:0] req;// request line to be asserted by a client reg [num_periph-1:0] gnt;// grant line to respond to each client reg data_rdy; // signal to strobe when data is ready reg [31:0] data; // data on bus endmodule module peripheral #(integer client_num) // peripheral number on bus (input module b, // input module which is the bus input wire clk, // input system clock wire read_req; // indicates this peripheral should read wire write_req); // indicates this peripheral should write reg [ 31:0 ] buffer; always (@posedge clk) begin if (read_req) begin wait (b.data_rdy); // reference module by port name buffer = b.data; wait (!b.data_rdy); end else if (write_req) begin req[client_num] = 1'b1; @(gnt[client_num]) b.data = buffer; b.data_rdy = 1'b1; @(negedge gnt[client_num]) b.data_rdy = 1b0; req[client_num] = 1'b0; end end endmodule module netlist; wire clk; bus b #(2) (clk); // instantiate the bus peripheral_0 #(0) (b, clk); // pass the bus hierarchically peripheral_1 #(1) (b, clk); // pass it to second peripheral endmodule Further proposals on specific LRM changes will be forthcoming. |
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