| Add Proposal | Add Analysis | Edit Class, Environment, or Release |
| Number | 459
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| Category | errata
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| Synopsis | 9.2: assignment variable_lvalue evaluation order question
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| State | open
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| Class | errata-discuss
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| Arrival-Date | Aug 31 2003
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| Originator | Shalom Bresticker <Shalom.Bresticker@motorola.com>
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| Release | 2001b: 9.2
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| Description |
9.2.1 on blocking assignments says, "If reg_lvalue requires an evaluation, it shall be evaluated at the time specified by the intra-assignment timing control. " 9.2.2 para. 3 on nonblocking assignments says, "If reg_lvalue requires an evaluation, it shall be evaluated at the same time as the expression on the right-hand side. The order of evaluation of the reg_lvalue and the expression on the right-hand side is undefined if timing control is not specified." Steven Sharp once wrote that he verified that the description in 9.2.2 is correct in Verilog-XL, even though the difference between evaluation time of reg_lvalue between blocking and nonblocking assignments seems illogical. The following questions remain: 1. If there is no timing control in a blocking assignment, is the order of evaluation of the reg_lvalue and the RHS specified? 2. The NBA paragraph says that reg_lvalue and the RHS are evaluated "at the same time" and also that their order of evaluation is not specified if there is no timing control. However, if they are always evaluated "at the same time" whether or not there is a timing control, then it would apparently seem that their order of evaluation is ALWAYS not specified, even if there IS a timing control. As a side-note, the current wording of these sections is unchanged from 1364-1995. A draft version of 1364-1995 had the same wording as in blocking assigments ("evaluated at the time specified by the intra-assignment timing control") used also to describe non-blocking assignments, but at some point it was changed to the present wording. This issue is a spin-off from #206. The result should be rewording of both paragraphs, clarifying the ambiguities, and using as similar or parallel wording as possible. Shalom |
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From: Shalom.Bresticker@motorola.com To: etf-bugs@boyd.com Cc: Subject: Re: errata/459: 9.2: assignment variable_lvalue evaluation order question Date: Sun, 14 Sep 2003 17:07:57 +0300 (IDT) I found that 5.6.3 and 5.6.4 also discuss the time of evaluation of the RHS and LHS of blocking and nonblocking assignments, and cross-reference to 9.2.1 and 9.2.2, respectively. I would add cross-references in the reverse direction as well. See below for more comments: > 9.2.1 on blocking assignments says, > > "If reg_lvalue requires an evaluation, it shall be evaluated at the time > specified by the intra-assignment timing control. " > > > 9.2.2 para. 3 on nonblocking assignments says, > > "If reg_lvalue requires an evaluation, it shall be evaluated at the same > time as the expression on the right-hand side. The order of evaluation > of the reg_lvalue and the expression on the right-hand side is undefined > if timing control is not specified." > > 1. If there is no timing control in a blocking assignment, is the order of > evaluation of the reg_lvalue and the RHS specified? 5.6.3 is worded as follows: "A blocking assignment ... computes the right-hand side value using the current values, then causes the executing process to be suspended ... When the process is returned (or if it returns immediately if no delay is specified), the process performs the assignment to the left-hand side ... The values at the time the process resumes are used to determine the target(s)." From this, I deduce that from the letter of the LRM, first the RHS is evaluated and then the reg_lvalue. (Although strictly speaking, that first sentence starts off, "A blocking assignment statement with a delay computes the right-hand side ...") > 2. The NBA paragraph says that reg_lvalue and the RHS are evaluated "at the same > time" and also that their order of evaluation is not specified if there is no > timing control. > > However, if they are always evaluated "at the same time" whether or not there is > a timing control, then it would apparently seem that their order of evaluation > is ALWAYS not specified, even if there IS a timing control. 5.6.4 also does not specify an order. It says, "The values in effect when the update is placed on the event queue are used to compute both the right-hand value and the left-hand target." So it seems correct to conclude that the order of evaluation of the right-hand value and the left-hand target is not specified even if there IS a timing control. -- Shalom Bresticker Shalom.Bresticker@motorola.com Design & Reuse Methodology Tel: +972 9 9522268 Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 441478 |
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