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| Number | 487
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| Category | errata
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| Synopsis | Unclear parameter type conversion rules (3.11.1 and 12.2)
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| State | open
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| Class | errata-simple
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| Arrival-Date | Sep 23 2003
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| Originator | sharp@cadence.com
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| Release | 2001b: 3.11.1, 12.2
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| Description |
The rules in 3.11.1 and 12.2 specify more or less that when a parameter has an explicit type, the value assigned to it by whatever means will be converted to that type. However, the meaning of this is not clear. It could be evaluated as a self-determined expression, and then the value converted to the type of the parameter. But this is not consistent with all other situations in Verilog. These are effectively assignments, and the evaluation of the value should be done in the context of the left hand side, i.e. the type of the parameter. I have been assuming that this was obvious, but it may not be. Here is a simple example: parameter [31:0] ip = 4'b1101 << 15; If the value is evaluated as self-determined, the width will be 4, and the value will overflow to 4'b0, and then be converted at the end to 0. If it is evaluated in context, the width will be 32, and the value will not overflow. It will be 32'b1101000000000000000, which is presumably what was desired. The same should apply to a parameter override with an expression. |
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| Audit-Trail |
From: "Brad Pierce" <Brad.Pierce@synopsys.com> To: <etf-bugs@boyd.com> Cc: Subject: Re: errata/487: Unclear parameter type conversion rules (3.11.1 and 12.2) Date: Tue, 23 Sep 2003 18:57:36 -0700 Parameter types are polymorphic and dependent on the type of the value assigned to the parameter? So, for example, if P is declared parameter [31:0] P = 4'b0000 it is really only 4 bits wide, not 32, and if it is overridden with 5'b00001, it is 5 bits wide? -- Brad From: "Francoise Martinolle" <fm@cadence.com> To: <etf-bugs@boyd.com>, <Brad.Pierce@synopsys.com> Cc: Subject: Re: errata/487: Unclear parameter type conversion rules (3.11.1 and 12.2) Date: Wed, 24 Sep 2003 11:01:34 -0400 According to the rules in section 12.2, the overridden value shall be converted to the type and the range of the parameter declaration. In the declaration, the parameter range is 32 bits regardless of what is the value on the left hand side. According to 12.2 the values assigned to the parameters are converted to the type and range of the declaration if any. This is new in 2001. In 1995, parameters did not have a type neither a range declared and it was taking the type and range of the expression on the last override. In your example, after final overridden the parameter value will be 32 bit wide and its value will be 32' bits with the LSB be a 1 Francoise ' At 06:10 PM 9/23/2003 -0700, Brad Pierce wrote: Precedence: bulk The following reply was made to PR errata/487; it has been noted by GNATS. From: "Brad Pierce" <Brad.Pierce@synopsys.com> To: <etf-bugs@boyd.com> Cc: Subject: Re: errata/487: Unclear parameter type conversion rules (3.11.1 and 12.2) Date: Tue, 23 Sep 2003 18:57:36 -0700 Parameter types are polymorphic and dependent on the type of the value assigned to the parameter? So, for example, if P is declared parameter [31:0] P = 4'b0000 it is really only 4 bits wide, not 32, and if it is overridden with 5'b00001, it is 5 bits wide? -- Brad From: Steven Sharp <sharp@cadence.com> To: etf-bugs@boyd.com, Brad.Pierce@synopsys.com Cc: Subject: Re: errata/487: Unclear parameter type conversion rules (3.11.1 and 12.2) Date: Wed, 24 Sep 2003 17:57:06 -0400 (EDT) > Parameter types are polymorphic and dependent on > the type of the value assigned to the parameter? If the parameter has no explicit type declared, then yes. This was always the case in Verilog-1995, since parameters could not have an explicit type declared in Verilog-1995. In Verilog-2001, it is legal to declare a type (integer, real, signed or unsigned vector with range) on a parameter declaration. In that case, its type is set by the declaration, rather than the value assigned. The cited sections (3.11.1 and 12.2) give detailed rules for determining the type of a parameter in all situations. > So, for example, if P is declared > > parameter [31:0] P = 4'b0000 > > it is really only 4 bits wide, not 32, and if it > is overridden with 5'b00001, it is 5 bits wide? Since you declared P with an explicit range [31:0], then no. But if you left the range off, then yes. It would change width when it changed value. That part is all clear. This erratum is about the details of value conversion when there is an explicit type declared and it is not the same as the value. Steven Sharp sharp@cadence.com From: Shalom.Bresticker@freescale.com To: etf-bugs@boyd.com Cc: Subject: Re: errata/487: Unclear parameter type conversion rules (3.11.1 and 12.2) Date: Sun, 12 Dec 2004 10:05:19 +0200 (IST) See 483 for additional relevant information. |
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