| Number | 522
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| Category | errata
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| Synopsis | A.2.2.3: delay2 and delay3 should be constant expressions
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| State | lrmdraft
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| Class | errata-discuss
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| Arrival-Date | Jan 05 2004
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| Originator | Shalom Bresticker <Shalom.Bresticker@motorola.com>
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| Release | 2001b
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| Description |
7.14.1 says, "The syntax for delays on gate primitives (including user-defined primitives; see Clause 8), nets, and continuous assignments shall allow three values each for the rising, falling, and turn-off delays. The minimum, typical, and maximum values for each delay shall be specified as constant expressions separated by colons. There shall be no required relation (e.g., min <= typ <= max) between the expressions for minimum, typical, and maximum delays. These can be any three constant expressions." In the BNF, these delays are expressed as "delay2" and "delay3". After the changes of issue 174, they now appear as (see A.2.2.3): delay3 ::= # delay_value | # ( mintypmax_expression [ , mintypmax_expression [ , mintypmax_expression ] ] ) delay2 ::= # delay_value | # ( mintypmax_expression [ , mintypmax_expression ] ) delay_value ::= unsigned_number | real_number | identifier These do not express that delay2 and delay3 should be constant expressions, which generally is expressed in the grammar wherever possible. delay_value cannot be changed because it is used elsewhere in non-constant contexts. I propose to add constant_delay_value ::= unsigned_number | real_number | parameter_identifier | specparam_identifier | genvar_identifier and change delay_value in delay2 and delay3 to constant_delay_value. I would have liked to change mintypmax_expression to constant_mintypmax_expresssion, but I see that Verilog-XL accepts hierarchical parameter references in delay2 and delay3, which are not allowed in constant_mintypmax_expression. -- Shalom Bresticker Shalom.Bresticker@motorola.com Design & Reuse Methodology Tel: +972 9 9522268 Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 441478 |
| Fix |
In 7.14.1, delete the statements that the delays are constant expressions. Specifically, DELETE the word "constant" twice in paragraph 1 in the following sentences: "The minimum, typical, and maximum values for each delay shall be specified as constant expressions separated by colons. There shall be no required relation (e.g., min <= typ <= max) between the expressions for minimum, typical, and maximum delays. These can be any three constant expressions." |
| Audit-Trail |
From: Steven Sharp <sharp@cadence.com> To: etf-bugs@boyd.com, Shalom.Bresticker@motorola.com Cc: Subject: Re: errata/522: A.2.2.3: delay2 and delay3 should be constant expressions Date: Mon, 5 Jan 2004 16:54:25 -0500 (EST) Just for reference, neither Verilog-XL nor NC-Verilog require these delays to be constant expressions. Steven Sharp sharp@cadence.com From: Stephen Williams <steve@icarus.com> To: etf-bugs@boyd.com Cc: Subject: Re: errata/522: Re: errata/522: A.2.2.3: delay2 and delay3 should be constant expressions Date: Mon, 05 Jan 2004 20:31:22 -0800 Steven Sharp wrote: > The following reply was made to PR errata/522; it has been noted by GNATS. > > From: Steven Sharp <sharp@cadence.com> > To: etf-bugs@boyd.com, Shalom.Bresticker@motorola.com > Cc: > Subject: Re: errata/522: A.2.2.3: delay2 and delay3 should be constant expressions > Date: Mon, 5 Jan 2004 16:54:25 -0500 (EST) > > Just for reference, neither Verilog-XL nor NC-Verilog require these delays > to be constant expressions. > > Steven Sharp > sharp@cadence.com ... And I've seen bug reports in the real world that suggest that people actually do change gate delays at run time. -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep." From: Shalom.Bresticker@motorola.com To: etf-bugs@boyd.com Cc: Subject: Re: errata/522: A.2.2.3: delay2 and delay3 should be constant expressions Date: Tue, 6 Jan 2004 10:33:07 +0200 (IST) Yes, you are both correct. I now saw that this came up in the discussions on issue #174. That is the reason we used the general 'identifier'. I also just found a mail from Adam Krolnik on July 15, 1998 which points this out. See http://boydtechinc.com/btf/archive/btf_1998/0248.html So, then apparently the BNF is correct and the text needs to be changed. The only place I find which says that the delays must be constant is 7.14.1 Shalom > > Just for reference, neither Verilog-XL nor NC-Verilog require these delays > > to be constant expressions. > > ... And I've seen bug reports in the real world that suggest that > people actually do change gate delays at run time. -- Shalom Bresticker Shalom.Bresticker@motorola.com Design, Verification & Reuse Methodology Tel: +972 9 9522268 Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 441478 Fix replaced by Shalom.Bresticker@motorola.com on Sun Feb 22 02:50:12 2004 In 7.14.1, delete the statements that the delays are constant expressions. Specifically, DELETE the word "constant" twice in paragraph 1 in the following sentences: "The minimum, typical, and maximum values for each delay shall be specified as constant expressions separated by colons. There shall be no required relation (e.g., min <= typ <= max) between the expressions for minimum, typical, and maximum delays. These can be any three constant expressions." |
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