| Add Proposal | Add Analysis | Edit Class, Environment, or Release |
| Number | 539
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| Category | errata
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| Synopsis | 15.3.6, 16.2.2: $nochange
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| State | open
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| Class | errata-discuss
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| Arrival-Date | Feb 10 2004
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| Originator | Shalom.Bresticker@motorola.com
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| Release | 2001c: 15.3.6, 16.2.2
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| Description |
16.2.2, in Table 63 contains the seemingly strange comment that $nochange is "not usually implemented in Verilog simulators". The comment is true in that Verilog-XL, NC-Verilog, and VCS all do not currently implement $nochange. They accept the syntax, but do nothing with it. Anyway, it seems like a strange comment because the LRM does not seem to treat it as an optional part of the language, but just like any other timing check which a tool is required to accept in order to be fully compliant with the language. Is an official IEEE standard the proper place for a comment about what is "usually implemented"? If $nochange is optional, then 1364 should simply say so. And any comment about the limited use or applicability of $nochange should be placed also in 15.3.6, and especially there, which is the main section describing $nochange. This was Tel Elkind's comment: $nochange was originally implemented for a now defunct timing analysis tool called Veritime. At the time, 1990, it wasn't felt $nochange was implementable in Verilog-XL, but it *was* implemented in Veritime, and so naturally Cadence included it in the Verilog language proposal to OVI that eventually went on to become the 1364 IEEE standard. When the 1364 timing committee developed the current chapters on timing checks it was felt that simulator technology was capable of implementing $nochange, and I'm surprised the wording wasn't changed in the latest standard. This would be an oversight as I think the intention was to encourage Verilog simulator vendors to implement $nochange. -- Shalom Bresticker Shalom.Bresticker@motorola.com Design & Reuse Methodology Tel: +972 9 9522268 Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 441478 |
| Fix |
Unknown |
| Audit-Trail |
From: Shalom.Bresticker@freescale.com To: etf-bugs@boyd.com Cc: Subject: Re: errata/539: $nochange Date: Tue, 3 Aug 2004 16:23:14 +0300 (IDT) ---------- Forwarded message ---------- Date: Wed, 9 Apr 97 21:24:48 -0400 From: Ted Elkind <elkind@cadence.com> To: john@simucad.com Cc: 1364core@galaxy.nsc.com, bob@simucad.com Subject: Re: Does $nochange apply to logic simulation? Hi John, $nochange was originally added to the Verilog language by Cadence (prior to Verilog being placed in the public domain) for Veritime. Verilog was modified to accept legal $nochange constructs without comment, while Veritime included them as part of its timing analysis. The Verilog-XL manual from Cadence was updated to include a section describing Veritime specific features of the language that had no effect in Verilog-XL, such as $nochange, the polarity operator in path definitions, and qualified paths (later functionally added to Verilog-XL under the name of SDPDs). During IEEE standardization of the Verilog language the description of $nochange somehow found its way into the 1364 standard as if it were an operational part of simulation. Implementation of $nochange in a logic simulator is possible but problematic. I am not aware of any Verilog simulators, including Cadence's, that have implemented $nochange, but perhaps someone else on the committee is more familiar with what other vendors have done. If you'd still like answers to your questions they can likely be found in the Veritime user's and reference manuals. Ted Elkind Cadence Design Systems From: Shalom.Bresticker@freescale.com To: etf-bugs@boyd.com Cc: Subject: Re: errata/539: $nochange Date: Tue, 3 Aug 2004 16:22:35 +0300 (IDT) ---------- Forwarded message ---------- Date: Wed, 09 Apr 1997 16:37:40 -0700 From: John Williamson <john@simucad.com> To: 1364core@galaxy.nsc.com Cc: bob@simucad.com Subject: Does $nochange apply to logic simulation? Dear IEEE, Simucad has been investigating the $nochange system task (page 14-21). When we run tests for $nochange in OVIsim, it appears that OVIsim ignores it. Is $nochange suppose to apply to logic simulation? Simcuad's users say it is being used in the Altera library. However, I noticed this old IEEE committee e-mail from Victor and John: Date: Fri, 6 Jan 95 13:05:13 -0500 From: uunet!cadence.com!berman (Victor Berman) To: uunet!chronologic.com!ieee1364, uunet!chronologic.com!jws Subject: Re: more Chapter 15 I have included the definition of $nochange for timing analyzis. Victor > From daemon@chronologic.com Thu Jan 5 21:16:45 1995 > Date: Thu, 5 Jan 95 18:05:15 PST > From: jws@chronologic.com > To: ieee1364@chronologic.com > Subject: more Chapter 15 > > There is still an open issue with $nochange (sec. 15.10 Timing Checks). $nochange is > ignored by simulators, but presumably means something to timing analyzers. Can anyone > at Cadence state what $nochange means to Veritime. I'm assuming that's the only timing > verifier that knows about it. > > I would propose that we put $nochange in the non-normative system task chapter, along > with the description of its arguments, which are currently struck-through in table 15-10. It > would also be a good idea to state what this is supposed to mean to a timing analyzer, if > anyone knows. > > John > ---------- If $nochange does apply to logic simulation, Simucad has the following question: 1) Are the end-points in the "violation region" included in the check? Below is the test we ran on OVIsim: ==================================== //title $nochange is allowed in ieee 1364 spec, page 14-21 `timescale 1ns / 100ps module top; reg data, clk; wire out; test xy(clk, data, out); initial begin $monitor("%d %b %b",$time,clk,data); clk = 'b0; data = 'b1; fork #100 clk = 0; #200 clk = 1; #300 clk = 0; #310 data = 1; #400 clk = 1; #500 clk = 0; #510 data = 0; #600 clk = 1; #620 data = 1; #700 clk = 0; #800 clk = 1; #820 data = 0; #900 clk = 0; #1000 clk = 1; #1090 data= 1; #1100 clk = 0; #1200 clk = 1; #1290 data= 0; #1300 clk = 0; #1400 clk = 1; #1500 clk = 0; #1550 data= 1; join #200 $finish; end endmodule module test(clk, data, out); input clk, data; output out; wire out; buf (out,clk); specify (clk => out) = (80); $nochange(posedge clk, data,0,0); $nochange(posedge clk, data,15,15); $nochange(posedge clk, data,-15,-15); $nochange(posedge clk, data,-110,-110); endspecify endmodule Below are the results from OVIsim: =================================== OVIsim 1.0 Apr 8, 1997 17:48:46 * Licensed Software - Confidential/Proprietary * * Copyright (c) Cadence Design Systems, Inc., 1985-1992. * * All rights reserved. This package contains confidential/proprietary * * information, property of Cadence Design Systems, Inc., or its * * licensors and may be used only in accordance with the Open Verilog * * International license agreement under which this package is provided.* * REVERSE-ASSEMBLY, REVERSE-COMPILATION, AND REVERSE-ENGINEERING * * PROHIBITED. * * RESTRICTED RIGHTS LEGEND * * Use, duplication, or disclosure by the Government is subject to * * restrictions as set forth in subparagraph (c)(1)(ii) of the * * Rights in Technical Data and Computer Software clause at * * DFARS 252.227-7013 or its equivalent. * * Unpublished -- rights reserved under the copyright laws of * * the United States. * * Cadence Design Systems, Inc. 555 River Oaks Parkway, San Jose, * * California 95134, USA. * Compiling source file "nochng03.v" Highest level modules: top 0 0 1 200 1 1 300 0 1 400 1 1 500 0 1 510 0 0 600 1 0 620 1 1 700 0 1 800 1 1 820 1 0 900 0 0 1000 1 0 1090 1 1 1100 0 1 1200 1 1 1290 1 0 1300 0 0 1400 1 0 1500 0 0 1550 0 1 End of OVIsim 1.0 Apr 8, 1997 17:48:51 |
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