| Add Proposal | Add Analysis | Edit Class, Environment, or Release |
| Number | 582
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| Category | errata
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| Synopsis | A.1.2, config BNF doesn't match examples in Section 13
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| State | open
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| Class | errata-discuss
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| Arrival-Date | May 10 2004
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| Originator | "Brad Pierce" <Brad.Pierce@synopsys.com>
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| Release | 2001b
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| Description |
In 13.1, the example is config cfg1; design rtlLib.top; default liblist rtlLib; instance top.a2 liblist gateLib; endconfig but the semicolons are not accepted by the BNF in A.1.2. In 13.5.2 there are even mixed examples like config cfg1; design rtlLib.top default liblist aLib rtlLib; endconfig The semicolons are not necessary for parsing, or even readability, so maybe they should just be optional? config_rule_statement ::= ... | ; -- Brad |
| Fix |
Unknown |
| Audit-Trail |
From: Steven Sharp <sharp@cadence.com> To: etf-bugs@boyd.com, Brad.Pierce@synopsys.com Cc: Subject: Re: errata/582: A.1.2, config BNF doesn't match examples in Section 13 Date: Mon, 10 May 2004 18:42:24 -0400 (EDT) This appears to be another of the 15 issues already brought up in issue 372. As Shalom has said, perhaps this issue should be broken up so that we can deal with the pieces separately. The missing semicolons look like errors to me. Terminating the lines with semicolons would be consistent with other comparable Verilog syntax. Certainly Verilog coders are in the habit of typing them. If we accept enhancement request 350, then the config syntax isn't part of the Verilog HDL syntax, so it is less important to be consistent with Verilog syntax. And as Brad says, the semicolons aren't needed for parsing since all of the lines start with keywords. But it does look to me like they were intended to be there. Steven Sharp sharp@cadence.com From: Steven Sharp <sharp@cadence.com> To: etf-bugs@boyd.com Cc: Subject: errata/582: another inquiry Date: Fri, 11 Jun 2004 13:07:48 -0400 (EDT) I am forwarding this query, which shows someone else concerned with this issue. ------------- Begin Forwarded Message ------------- Date: Thu, 10 Jun 2004 06:48:27 +0000 From: Pooja Maheshwari <mpooja@agere.com> X-Accept-Language: en MIME-Version: 1.0 To: Steven Sharp <sharp@cadence.com>, stuart@sutherland-hdl.com CC: Pooja Maheshwari <mpooja@agere.com> Subject: Queries in Verilog-2001 std. Hello Steve/Stuart, I found some discrepancy in config section ( Clause 13 of IEEE1364-2001). In config section, design statement and config_rule_statements are allowed. According to BNF ( in tables 13.4 - 13.9 ) (*) a ";" is expected after design statement. (*) no ";" should be there after config rule statement (default liblist clause, instance clause, etc.) In examples, (*) 13.3.2 ";" is used after both design and config rule statements ( config bot, config top). (*) 13.5.2 ";" is not used in design statement but used in config rule statement ( config cfg1, cfg2, etc.). My question is, whether ";" should be there after design statement, or after "config rule statement" or both. Thanks, Pooja ------------- End Forwarded Message ------------- Steven Sharp sharp@cadence.com |
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