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| Number | 590
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| Category | enhancement
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| Synopsis | vector version of ?: operator
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| State | open
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| Class | enhancement
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| Arrival-Date | Jun 14 2004
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| Originator | Shalom Bresticker <Shalom.Bresticker@freescale.com>
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| Release | 2001b
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| Description |
This is a spinoff of issue 411. (Or more likely, 411 was a spinoff of this...) In the conditional operator, a ? b : c, a is taken as a scalar value. The result is either all of b or all of c. A very frequent need is a bit-wise multiplexer operation with separate controls for each bit. Suppose a is a vector now. Today, I have to write that as (a & b) | (~a & c) The request is to define a conditional operator with a vector condition instead of a scalar condition, and each bit of the vector condition is applied to the corresponding bits of the input expressions. Steven Sharp said they already have something like this internally. Shalom |
| Fix |
Unknown |
| Audit-Trail |
From: Steven Sharp <sharp@cadence.com> To: etf-bugs@boyd.com, Shalom.Bresticker@freescale.com Cc: Subject: Re: enhancement/590: vector version of ?: operator Date: Tue, 22 Jun 2004 20:05:18 -0400 (EDT) >Steven Sharp said they already have something like this internally. Just for clarification, this is something that is created by an internal transformation in the compiler, not something that can be written in the Verilog source. Steven Sharp sharp@cadence.com |
| Unformatted |
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