| Number | 627
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| Category | errata
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| Synopsis | 5.4.1(2): "time step 1" should be "0" ?
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| State | lrmdraft
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| Class | errata-simple
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| Arrival-Date | Sep 26 2004
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| Originator | Shalom Bresticker <Shalom.Bresticker@freescale.com>
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| Release | 2001b
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| Description |
Following up on the previous issue, 5.4.1(2) shows the following: "initial begin a <= 0; a <= 1; end When this block is executed, there will be two events added to the nonblocking assign update queue. The previous rule requires that they be entered on the queue in source order; this rule requires that they be taken from the queue and performed in source order as well. Hence, at the end of time step 1, the variable a will be assigned 0 and then 1." It appears to me that the last sentence should say "simulation time 0" or at least "time step 0" instead of "time step 1". Shalom -- Shalom Bresticker Shalom.Bresticker @freescale.com Design & Verification Methodology Tel: +972 9 9522268 Freescale Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 5441478 [ ]Freescale Internal Use Only [ ]Freescale Confidential Proprietary |
| Fix |
Propose to CHANGE in 5.4.1(2) FROM "time step 1" TO "simulation time 0". |
| Audit-Trail |
Fix replaced by Shalom.Bresticker@freescale.com on Mon Oct 18 01:16:10 2004 Propose to CHANGE in 5.4.1(2) FROM "time step 1" TO "simulation time 0". |
| Unformatted |
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