| Add Proposal | Add Analysis | Edit Class, Environment, or Release |
| Number | 654
|
| Category | errata
|
| Synopsis | 14.2.3: specify block edge-sensitive path description with
|
| State | open
|
| Class | errata-discuss
|
| Arrival-Date | Mar 03 2005
|
| Originator | Shalom.Bresticker@freescale.com
|
| Release | 2005: 14.2.3
|
| Description |
I received a behavioral model of a memory which includes specify blocks. The interesting lines look like this: specify specparam trstq = 0.000; (negedge reset_b +=> (q[0] : 1'bx)) = (trstq); endspecify This is an edge-sensitive delay path description which says that when there is a negative edge on reset_b, then there is a delay of value trstq from 1'bx to q[0]. Our lint tool did not accept this, saying that the syntax is illegal, because of the + sign before =>, which according to the BNF is only allowed on simple delay path descriptions, not on edge-sensitive path delay descriptions. They are correct about the BNF. The 1364 LRM also shows +=> only on simple paths. Same for Verilog-XL documentation. If you want to use the polarity symbol on edge-sensitive paths, you have to put it before the colon( +: or -: ) (not a smiley). But all 3 simulators that we have accept the code as written by our memory group, who are apparently used to writing it that way all the time. The lint tool vendor indicated that another simulator that he checked gave a warning. Should this syntax be legal? What does it mean? |
| Fix |
Unknown |
| Audit-Trail |
From: Steven Sharp <sharp@cadence.com> To: etf-bugs@boyd.com, Shalom.Bresticker@freescale.com Cc: Subject: Re: errata/654: 14.2.3: specify block edge-sensitive path description with polarity Date: Thu, 3 Mar 2005 13:55:19 -0500 (EST) >But all 3 simulators that we have accept the code as written by our memory group, >who are apparently used to writing it that way all the time. > >Should this syntax be legal? What does it mean? I would guess that the simulators are completely ignoring the +. Even for simple delay path descriptions, it has no effect on the behavior of a simulator. The tools probably throw it away as soon as they see it, without worrying about what kind of path this is. Steven Sharp sharp@cadence.com From: Shalom.Bresticker@freescale.com To: Steven Sharp <sharp@cadence.com> Cc: etf-bugs@boyd.com Subject: Re: errata/654: 14.2.3: specify block edge-sensitive path description with polarity Date: Thu, 3 Mar 2005 23:32:37 +0200 (IST) I agree that in practice the simulators ignore the polarity operator. In principle, a different type of tool might relate to it. Again, the problem is that it is not allowed by the BNF, but some people do write that way, and the simulators do accept it, but not all tools. Shalom On Thu, 3 Mar 2005, Steven Sharp wrote: > > >But all 3 simulators that we have accept the code as written by our memory > group, > >who are apparently used to writing it that way all the time. > > > >Should this syntax be legal? What does it mean? > > I would guess that the simulators are completely ignoring the +. Even > for simple delay path descriptions, it has no effect on the behavior of > a simulator. The tools probably throw it away as soon as they see it, > without worrying about what kind of path this is. > > Steven Sharp > sharp@cadence.com > -- Shalom Bresticker Shalom.Bresticker @freescale.com Design & Verification Methodology Tel: +972 9 9522268 Freescale Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 5441478 [ ]Freescale Internal Use Only [ ]Freescale Confidential Proprietary |
| Unformatted |
polarity |
Hosted by Boyd Technology