From: Adam Krolnik (krolnik@lsil.com)
Date: Mon Jul 19 1999 - 14:13:30 PDT
Stuart Sutherland wrote:
>
> BTF,
>
> I received the following example from a colleague (the example is derived
> from the OVI test suite for Verilog):
>
> {i, 2'b0} << -1; //where i is an integer
>
> Per my understanding of the 1364-1995 LRM, this should have done a left
> shift some large number of times (2's complement of 1, treated as an
> unsigned 32-bit value). The data type of "i" should not have any bearing.
>
> It seems Verilog-XL will actually do a right shift by 1. That is, the
> negative shift operand changed the shift direction.
>
In the spirit of Perl, excellent!
Now, can we get b[-1] to access the bit at the msb (b[7] :) ?
reg [7:0] b;
<p> Adam
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