From: Stuart Sutherland (stuart@sutherland.com)
Date: Mon Jul 19 1999 - 12:30:06 PDT
BTF,
I received the following example from a colleague (the example is derived
from the OVI test suite for Verilog):
{i, 2'b0} << -1; //where i is an integer
Per my understanding of the 1364-1995 LRM, this should have done a left
shift some large number of times (2's complement of 1, treated as an
unsigned 32-bit value). The data type of "i" should not have any bearing.
It seems Verilog-XL will actually do a right shift by 1. That is, the
negative shift operand changed the shift direction.
Is this the correct behavior?
Stu
<p>Attachment Converted: "C:\Documents and Settings\stefen\Application Data\Qualcomm\Eudora\clhuang1.vcf"
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Stuart Sutherland Sutherland HDL Inc.
stuart@sutherland.com 22805 SW 92nd Place
phone: 503-692-0898 Tualatin, OR 97062
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